surreyian
Member level 3
esd protection circuit
when doing esd design for vdd/vss, we use the gate grounded NMOS. why is it so?
i also came across design that have a R at its gate and tie to GND. what is the difference? what is the advantage of using the R? is it to provide a low impedance path? or is it to prevent ruptures of the oxide.
thanks
when doing esd design for vdd/vss, we use the gate grounded NMOS. why is it so?
i also came across design that have a R at its gate and tie to GND. what is the difference? what is the advantage of using the R? is it to provide a low impedance path? or is it to prevent ruptures of the oxide.
thanks