Qus- when doing esd design for vdd/vss, we use the gate grounded NMOS. why is it so?
Ans- To protect the circuit from ESD event by using either up-and-down diode or GGNMOS.
Qus- i also came across design that have a R at its gate and tie to GND. what is the difference? what is the advantage of using the R? is it to provide a low impedance path?
Ans- resitor provide high resistance path so high current (ESD is current phenomenon) will not pass through the PMOS/NMOS device and it can be protected. As you know, for excess current already we design a path of low resistance.