Urgent: Frequency division

[olajide85]

I have been having issue on testing this code on the altera board. ths code is meant to convert 5oMHz to 1Hz. after testing it on the board, I discovered it is nopt working on the altera board. I need help on this. this is the code. I will appreciate your urgent response.






ENTITY FDIVIDER IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
clk : IN STD_LOGIC;
clkout : OUT STD_LOGIC
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!

END FDIVIDER;


-- Architecture Body

ARCHITECTURE FDIVIDER_architecture OF FDIVIDER IS


BEGIN
PROCESS (clk)
VARIABLE count : INTEGER RANGE 0 TO 25000000;
BEGIN

if(clk'event and clk='1') then

if(count=25000000)then
count:=0;
clkout<='0';
else
count := count+1;
clkout<='1';


END IF;
END IF;
END PROCESS;

END FDIVIDER_architecture;

 

[lucbra]

Reset and initialisation of clkout?

begin
   if reset = '1' then
      clkout <= '0';
   elsif rising_edge(clk) then
--etc

Also, be aware that clkout is only changing state for a very, very short time

 

[alexan_e]

olajide85, your code creates a very short low pulse (1/25000000 sec duration) and then returns to High again, is that what you want?
I think what you want is to make the output 1 after 25000000 clocks , then 0 after 25000000 more clocks , then 1 after 25000000 more clocks etc.

Alex

 

[olajide85]

what I want is to convert 50MHz to 1Hz with the codes above so that i can test the design on the altera board....any modification to it?

---------- Post added at 19:46 ---------- Previous post was at 19:36 ----------

alexan_e, can you modify it for me?

 

[alexan_e]

Use a variable out_buf,
then when the count is 25000000 use out_buf:= not out_buf;
then just assign this value to the output clkout<= out_buf;

Alex

 

[olajide85]

please am new to this.can you help me edit it on the code posted?

---------- Post added at 19:59 ---------- Previous post was at 19:54 ----------

50MHz to 1Hz using vhdl.

 

[alexan_e]

The point is for you to learn and I have already explained what you need to do , it is not that hard.

This code gives only a pulse because

if(count=25000000)then
count:=0;
clkout<='0'; -- this will be true only for one clock
else
count := count+1;
clkout<='1'; -- and then the value will return to this until you reach 25000000 again

You can do something simpler for you, when the count is 25000000 set clkout<='1';
and when count is 50000000 set clkout<='0';

 

[olajide85]

i tried it but getting errors. Can you edit it on the one i posted in the forum.

 

[alexan_e]

Take a look at these

https://www.edaboard.com/threads/215570/#post917906

VHDL coding tips and tricks: Clock Frequency converter in VHDL

 

[imbichie]

Hi Olajide85,

I think this should work... See the code below....

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY FDIVIDER IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
clkout : OUT STD_LOGIC
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END FDIVIDER;

-- Architecture Body

ARCHITECTURE FDIVIDER_architecture OF FDIVIDER IS
begin
process (rst,clk)
variable count : integer range 0 to 49999999 := 0;
begin
if(rst = '1') then
count := 0;
clkout <= '0';
elsif(rising_edge(clk)) then
if(count < 25000000)then
count := count + 1;
clkout <= '0';
elsif(count >= 25000000 and count <= (49999999 - 1)) then
count := count + 1;
clkout <= '1';
elsif(count = 49999999) then
count := 0;
end if;
end if;
end process;

END FDIVIDER_architecture;