Unreached status in a FSM

[Dijskstra]

Hi all,


Consider this code

process (clk, reset)
begin
    if (reset = '1') then
        pr_state <= idle;
    elsif rising_edge(clk) then
        pr_state <= nx_state;
end process;


process (pr_state)
begin
    case pr_state is
        when idle => 
                output_pin <= 'Z';
                nx_state <= request_low;

        when request_low =>
                output_pin <= '0';  -- send '0' to output pin

                reset_counter <= '1'; reset to a counter that waits a fixed amount of time
                if (ready_counter = '1') then   -- while counter not zero
                    nx_state <= request_low;  --  stay in the current state
                else
                    nx_state <= request_high; -- else jump to next state
                end if;

        when request_high =>
                    output_pin <= '1'  -- send '1' to output pin
                    .
                    .
                    .
--         other status
                    .
                    .
                    .
    end case;
end process;

When I try to synthesize ISE outputs in the console:



-

------------------------------------------
State | Encoding
-------------------------------------------~
idle | 0000000
request_low | 0000001
request_high | unreached
.................. | unreached
.................. | unreached
.................. | unreached

Why "unreached" ?


Thank you

Anders

 

[shaiko]

Try to rewrite your FSM in a single clocked process (synchronous FSM)
Otherwise, if you choose to design an asynchronous FSM you must include ALL the FSMs (input and output) signals in the sensitivity list when you simulate it. Also, you must assign them a default value.

Anyways, I suggest you use the single process synchronous style...

 

[TrickyDicky]

You only posted a snippet, so I am going to make assumptions.
I can only guess that ready_counter is always high, so the other states cannot be reached.

And as shaiko said, your snippet is not idea code for a 2 process state machine.

 

[hpb]

Hi Dijskstra ,

Please refer to below link. This may help you..
**broken link removed**