// VerilogA for Verilog_A, data_readout, veriloga
`include "constants.vams"
`include "disciplines.vams"
module module_filereader (out);
output out;
electrical out;
parameter real period = 1/10k;
parameter integer maxcount = 480;
integer dataread, cnt;
real mydata1, mydata2;
real datacol [maxcount-1:0];
analog begin
@(initial_step("tran")) begin
cnt = 0;
dataread = $fopen("/mnt/cnm/khan/Amir_IC/Building_block/One_column_image1.csv","r"); //opening file readable access
end
@(timer(0, period )) begin
cnt = cnt+1;
end
while( cnt < maxcount ) begin
mydata1 = $fscanf(dataread,"%f", datacol[cnt]);
// mydata1 = $fscanf(dataread,"%f",cnt);
end
$debug("\nThe value of variable mydata1 is %f",mydata1);
@(final_step) $fclose(dataread);
V(out) <+ transition(mydata1, 1n, 1n, 1n);
end
endmodule