zaixq said:you can refer allen's book about comparator design
Steven De Bock said:I bought this book from R. J. Baker: CMOS Circuit design, Layout and Simulation. I think it is a rather interesting book, covering most topics about analog/digital design.
There is a chapter about nonlinear circuits, describing a comparator-circuit with 3 stages. The first being a preamplifier, the second stage being a decision circuit (2 cross coupled devices) and the third stage being an output buffer (a simple differential amplifier with a current mirror load).
The problem is that I'm not sure in how to dimension the transistors in this kind of topology. Propagation speed is a very crucial factor in my comparator design.
Is anyone familiar with this kind of comparator topology? Is he/she willing to give me some pointers in where to find a more elaborate explanation about the workings of this type of comparator?
Thank you very much!
dear allSyukri said:Maybe i give the picture...
Soory if u are not being able to download it..