Finding Rdson for Mosfet (CMOS) in 22nm

[aguntukbd]

Hello,
I need to size LDPMOS and LDNMOS in 22nm technology for switching circuit. Now How can I find the RDSon in cadence virtuoso for the MOSFETs? DC operating point is not giving me any value for it. Is there any way to simulate? Can anyone elaborate and explain me please?

 

[dick_freebird]

Just set up the FET in the configuration that Rds(on) is specified at.
This could be "peak current" (at some dynamic load) or could be a
"VOH/VOL" type interest (conduction losses @ load) or maybe this
is just an exercise and comes with its own description.

Impose voltages, measure currents, do math.

Many times a "transistor" is not a single transistor when you get
down to it. Realities may require that the drift region be modeled
as a JFET, and then the MOSFET params are irrelevant. Get used
to dealing with the devices on the basis of their accessible,
terminal voltages & currents.

 

[aguntukbd]

Just set up the FET in the configuration that Rds(on) is specified at.
This could be "peak current" (at some dynamic load) or could be a
"VOH/VOL" type interest (conduction losses @ load) or maybe this
is just an exercise and comes with its own description.

Impose voltages, measure currents, do math.

Many times a "transistor" is not a single transistor when you get
down to it. Realities may require that the drift region be modeled
as a JFET, and then the MOSFET params are irrelevant. Get used
to dealing with the devices on the basis of their accessible,
terminal voltages & currents.

I did not get fully what you said.

Just set up the FET in the configuration that Rds(on) is specified at.

For integrated 22nm technology, Rds(on) is not specified there. Therefore, I have to extract it on my own depending on my current requirement (which I know). Now I just want to get the Rds(on) for input and supply voltage and based on current output requirement I will choose the size relatively. I am using Cadence virtuoso. Do you know simple testbench setup for getting the Rds(on) for any FET?

 

[timof]

Apply zero voltage to source and bulk, maximum Vgs to the gate, and small Vds (50 mV or 100 mV) to the drain.

Divide Vds by Ids - you will get Rdson.

Rdson is inversely proportional to W (gate width).

 

[D.A.(Tony)Stewart]

Compute it the same way one does any logic chip for Rol and Roh = RdsOn and same for Voh difference.
Use the industry standard test current for each Vcc (aka Vdd) unless you define your own thresholds.

 

[dick_freebird]

I did not get fully what you said.

I get that a lot.

What I recommend is that you look up the confusing bits at
sources you like, and see if those things make sense or not.