CMOS IC working in a wide supply voltage

[Junus2012]

Hello,

I see from the industry chip, for instance, op-amp chips that the range of supply voltage can be a wide range. For example, consider the analog comparator MCP6549 from Microchip Technology. The supply voltage is from 1.6 V to 5.5 V.

I am designing with CMOS 0.35 µm standard process, but the usual range I have in my design for proper operation is maximum between 2.8 V to 3.6, else I start to have problem in my cascoded branches for low voltage and for the higher voltage I will be restricted by the technology so I am not allowed to use higher voltage like 5 V.

So how the industrial chips are making the supply voltage wide, do they use internal LDO or something related to the technology?

Thanks

 

[dick_freebird]

Still plenty of 5V technologies in production, much easier to use a
naturally capable process (if you can get the performance - and if
you're setting the goals, with a mature process, that should be no
prob.

You can protect the front end and stack the back end especially on
SOI (or triple well). Tall stacks in basic JI suffer from NMOS body
effect and cascoding cannot help the Vdb limit (which may be more
than Vds, Vdg reliability based limits, but often goes unquantified).

What sets the technology choice? Not like 0.35u is a superstar in
any aspect.

 

[Junus2012]

Still plenty of 5V technologies in production, much easier to use a
naturally capable process (if you can get the performance - and if
you're setting the goals, with a mature process, that should be no
prob.

You can protect the front end and stack the back end especially on
SOI (or triple well). Tall stacks in basic JI suffer from NMOS body
effect and cascoding cannot help the Vdb limit (which may be more
than Vds, Vdg reliability based limits, but often goes unquantified).

What sets the technology choice? Not like 0.35u is a superstar in
any aspect.

Thanks freebird,

As I understood from you that industry use the 5 V still, but how this technology accept a voltage of 1.6 V for example.

Generally can I use smaller voltage than recommended by technology?, like in my case with 0.35 µm, can I propose design with 1.8 V on this technology?

 

[Dominik Przyborowski]

Almost every process is providing so-called I/O devices, which are mosfets using thicker oxide. Usually, 0.35um process provides I/O devices with nominal 5V.
And yes, you can use lower supply as long as your circuit is operating. Academia is fighting with Circuits operating down to 0.3V. Industry has to deal with supply between USB (5V) and battery (1.5V).

 

[Junus2012]

Almost every process is providing so-called I/O devices, which are mosfets using thicker oxide. Usually, 0.35um process provides I/O devices with nominal 5V.
And yes, you can use lower supply as long as your circuit is operating. Academia is fighting with Circuits operating down to 0.3V. Industry has to deal with supply between USB (5V) and battery (1.5V).

Thanks Dominik,

You mean to say that I/O devices use higher voltage, but what about the internal circuits?

 

[nitishn5]

You want a circuit that works from 5.5V all the way down to 1.6V and you are facing headroom issues since the 5V devices you used have too large a Vth to operate properly at 1.6V supply.

Process selection is the start. You want a cheap process that has the devices you want. For example TSMC 0.18um process has flavours with 3.3V I/O devices or 5V I/O devices. And this is usually the case with most process nodes, the I/O devices have multiple flavours.

A "simple" solution to the voltage range problem could be to use a simple charge-pump / voltage doubler which gets enabled once the supply is less than say 2.5V. This can provide a higher supply rail when the actual supply is too low. No extra masks or anything but extra circuitry.
Or you can use some specialty devices such as low Vt devices and what not. But this is at the cost of extra masks.
Or you could use some of those low voltage supply circuits and see if those can be modified to operate over the larger range.


Also, for standalone analog parts such as opamps or comparators, there aren't usually any "internal" circuits or any digital which would require an LDO or anything. If any digital is still present, it could just use the I/O devices and operate at a much lower frequency to deal with the timing.

 

[dick_freebird]

You can use "I/O" devices in the "core". You may see some rules imposed
(like latchup rings) if the DRC is unsophisticated, that hurts only area.

The difference in VT between 0.6u ("5V" lowest L I've seen, and best pad
it a little for analog) and 0.35u is probably 100mV or so. Not the killer.
You'd just be a bit deeper into subthreshold but that's where you want
to be anyway, for DC qualities. Speed, you'll suffer.

There are "over the rail" op amps which employ charge pumps (and
noise mitigation tricks).

 

[Dominik Przyborowski]

You mean to say that I/O devices use higher voltage, but what about the internal circuits?

Everything depends on your needs.
Level shifters, multiple domains, LDOs are used for some purposes.

 

[Junus2012]

Dear friends,

Thank you very much for your answers and nice explanation you provided me.

Yes the 0.35 µm technology I am using it supports the 5 V I/O,

But the core module is still 3.3 V, so do you mean that 5 V I/O pads will clamp the 5 V to 3.3 V ?,

Thank you

 

[dick_freebird]

"Library pads" might have in-built ESD circuitry (just diodes, or more)
but there should be 5V pad family if there's 5V devices. I/O libraries may
be separate from core. Doing the right thing for supplies is key.

 

[nitishn5]

I think there is some misunderstanding here...

In your original question, you mention having to use 2.8V to 3.6V supply. Is this range coming from the system specifications or from the process selection or from the design?

Also what do you mean by "core module"?