Ok, let me try.
This is the original design:
DFF DFF1 (.clk(CLK), .d(D1), .q(Q1));
DFF DFF2 (.clk(CLK), .d(D2), .q(Q2));
D2 = f(Q1); // f is the combinational logic, and has delay of 10ns, for example;
After skew of clocks, the new design is:
CLK_skew = BUF (CLK);
DFF DFF1 (.clk(CLK), .d(D1), .q(Q1));
DFF DFF2 (.clk(CLK_skew), .d(D2), .q(Q2));
D2 = f(Q1); // f is the combinational logic, and has delay of 10ns, for example;
Between the old design and the new design, the only change is DFF2 clock line is delayed, comparing to DFF1's clock. Now if you plot the timing diagram and do some analysis, you should be able to reach the conclusion that you can increase the clock frequency and the circuit still works!