Timing optimization of scan paths

[jjean]

Hi,

I have a question regarding scan insertion.
How is timing for scan paths taken care of?While doing synthesis, we constrain the inputs/outputs of the design for certain input/output delays.How are scan inputs and scan outputs constrained?

Appreciate any help.

 

[jaydip]

why do you want to check timing for scan paths?? scan in, scan out, scan enable are not going to be connected to any combo loop as such, right? ..

 

[jjean]

Do you mean that since there is no combo logic between the scan flops in scan mode,setup violations will not occur and so,even if the scan paths are not constrained,timing would not be a issue? But hold violations can occur in the scan path and they have to be taken care of,right?
Also if the i/o ports are not constrained,then a default clock with zero i/o delay is taken which may not be correct since the clock with respect to which it should be constrained would actually be different.
Since scan insertion is done on the constrained netlist,can the scan paths be taken care of only in the backend?

Thanks

 

[rhythmrain]

Do you mean that since there is no combo logic between the scan flops in scan mode,setup violations will not occur and so,even if the scan paths are not constrained,timing would not be a issue? But hold violations can occur in the scan path and they have to be taken care of,right?
Also if the i/o ports are not constrained,then a default clock with zero i/o delay is taken which may not be correct since the clock with respect to which it should be constrained would actually be different.
Since scan insertion is done on the constrained netlist,can the scan paths be taken care of only in the backend?

Thanks

In Scan Mode, setup violations will not a issue, but hold violations should be taken care of. For violations occured at SIN port of flops, so just add delay cells before SIN. In Shift Mode, setup violations also not a big issue, but when fixing hold violations, we should take care of those violations related to data input of Flops. If add delay cells before D, may induce setup violations in normal function mode.
And we can also ajust clock tree to fix hold violations.


Generally, scan paths only need to be taken care of after post-routing.

 

[jjean]

Thanks a lot...

 

[ys82]

you can set some input/output delay on scan_in/scan_out. I think the ATE tester can give the reference value

 

[xinsu]

normally,scan shift/scan capture constraint will cover scan path,if you just want optimize scan path,you can use these constraint to opt design,but you should be careful donot touch function path

 

[Kaisia]

In Scan Mode, setup violations will not a issue, but hold violations should be taken care of. For violations occured at SIN port of flops, so just add delay cells before SIN. In Shift Mode, setup violations also not a big issue, but when fixing hold violations, we should take care of those violations related to data input of Flops. If add delay cells before D, may induce setup violations in normal function mode.
And we can also ajust clock tree to fix hold violations.


Generally, scan paths only need to be taken care of after post-routing.

could you give more information about how to adjust clock tree to fix those scan hold violations?

 

[srihari_adem]

could you give more information about how to adjust clock tree to fix those scan hold violations?

hold violations in scan will occur during shift phase where Q is connected to SI .
Hold violations can also occur in capture phase where Q is connected to D without any combo.
Remember same path can't cause both setup and hold violations to one endpoint.
We can add a delay cell near SI to increase fix the hold violation. This will affect the setup by any means
We can also pre-pone the capture clock or postpone launch clock to fix hold violation. In this case you need to be careful about setup checks.