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# Timing loop in my RTL design

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#### Prasandh92

##### Newbie
Hi,

I am seeing timing loops in my design? Can anyone help me in understanding why do I see timing loops? How do I fix them?

Hi,

I am seeing timing loops in my design? Can anyone help me in understanding why do I see timing loops? How do I fix them?

Hi,
Timing loops are created when your code is written.
Example code with a loop.
assign y0 = n0 & s0;
assign n0 = y0 & r1;

The error is created when the logic cone for y0 contains the signal (n0).
And the logic cone for n0 contains the signal (y0).

When you write your logic you should always consider the logic cone that you are creating for every signal. This will improve your finding timing problems early as well, this will come with experience.

another example of a loop that students often make is the following

Code Verilog - [expand]1
2
3
reg a;
always @(*)
a = a +1;

If a flop is present and the output feeds back to combo and then into the flop, is that still a problem?

If a flop is present and the output feeds back to combo and then into the flop, is that still a problem?
Yes, it is a problem, because always block is not clocked. As you may see, it has all the signals in its sensitivity list @(*) as opposed to @(posedge clk).
When you have a signal that is "self referenced" you have a combinatorial (logic/timing) loop. Try to imagine how would behave an actual digital circuit that gets it's inputs from its outputs. It'll go in some run away craziness.

It is OK to self reference if the value of a signal depends on the previous value of itself.
Code:
reg a;
always @(posedge clk)
a = a +1;
In this case, a will increment each cycle.

Code:
assign y0 = n0 & s0;
always @(posedge clk) n0 = y0 & r1;
Next n0 is r1 & y0, while y0 is s0 and previous value of n0

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