Nandy
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timing eco
In netlist timing closure period, ASIC designers have to do a lot of timing ECOs
according to timing violations report file. Timing ECO process is to fix setup or hold timing violations without changing RTL functions.
It can be inserting buffers inverts or increasing/decreasing cells drive strength or duplicating the heavy fanout cells to off-load fanouts.
But the timing violations report file normally gives hundreds thousands of violated paths and manually fixing even one path takes long time. Making things more complicated is a lot of paths have a lot shared cells in sub-paths.
New release of GOF v2.095 can handle timing ECO efficiently. It can parse synopsys PrimeTIme timing violation report file. And feed violated paths into GOF ECO flow automatically. Users have very clear view of the violated path connectivity and relation with other paths in a schematic.
Check one example of Timing ECO
https://www.nandigits.com/timingeco.htm
Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.
In netlist timing closure period, ASIC designers have to do a lot of timing ECOs
according to timing violations report file. Timing ECO process is to fix setup or hold timing violations without changing RTL functions.
It can be inserting buffers inverts or increasing/decreasing cells drive strength or duplicating the heavy fanout cells to off-load fanouts.
But the timing violations report file normally gives hundreds thousands of violated paths and manually fixing even one path takes long time. Making things more complicated is a lot of paths have a lot shared cells in sub-paths.
New release of GOF v2.095 can handle timing ECO efficiently. It can parse synopsys PrimeTIme timing violation report file. And feed violated paths into GOF ECO flow automatically. Users have very clear view of the violated path connectivity and relation with other paths in a schematic.
Check one example of Timing ECO
https://www.nandigits.com/timingeco.htm
Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode.