[SOLVED] Timing difference from pre-Place to Place DB

[ajaytronic]

Hi,

I am new to physical design world. I have some concern regarding the preplace timing & timing after placement. My timing were completely clean before pre-place stage - which shows perfectness of timing constains. After placement, the timing got very worse. (WNS is more than around -200 ns and violation path are more than 60k.) I have checked these violation, almost violation are coming in scan chain path.

I would like to know what got wrong in my placement. How to improve the scan-chain path timing?
BTW just to add, I am working on multi-power domain chip and floorplan cannot be changed.

Please share your experience. Also share if you have any idea to overcome of this issue.

Thanks,
Ajay

 

[cop02ia]

Scan-chains can be rewired (remove scan chain before placement & re-insert them after placement).
This makes the scan-chains follow a shorter path instead of crossing each other.
Look for "scan-chain removal" documentation for details.

Best regards,
I-FAB