Hi all,
I am working xilinx's tools ISE 6.1, I have simulated various VHDL codes using ModelSim and Aldec simulator. I have successfully synthesised them too with ISE but I dont know about timing constraints, could anybody refer me tutorial on it and associated terms like : clock to pad and pad to setup etc.
hi fakeha_s,
But it didnt help me to understand where, why and how should i specify timing constraints. could you send me a link from where i can get more abt it