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Timing Constraints in synthesis

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nlulani

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Hi all,
I am working xilinx's tools ISE 6.1, I have simulated various VHDL codes using ModelSim and Aldec simulator. I have successfully synthesised them too with ISE but I dont know about timing constraints, could anybody refer me tutorial on it and associated terms like : clock to pad and pad to setup etc.

thanks in advance

Nitin [/b]
 

fakeha_s

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from xilinx website you can get the relevant pdf document
 

nlulani

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hi fakeha_s,
But it didnt help me to understand where, why and how should i specify timing constraints. could you send me a link from where i can get more abt it

thanks and regards,
Nitin
 

echo47

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Have you read the Constraints Guide? That PDF file is in your ISE documents folder.
Chapter: Constraint Types. Section: Timing Constraints.
 

soccer

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timing constraints is very important for synthesis. you can refere to those books of "timing" for detail.
 

nlulani

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soccer said:
timing constraints is very important for synthesis. you can refere to those books of "timing" for detail.

Can you suggest me names of those books or refer any if availble for download from eda

thanks
 

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