stevenv07
Member level 2
Hello everyone,
I have a digital block. I implemented it as a hard macro, and extracted the timing model .lib.
Then, I instantiated this block into a top module (the top module only has this macro, and I/O pads), and do PnR.
In the SDC file, I just set input and output delays associated with this hard macro.
My question is how to check its timing at the top level? and what types of timing should I check (in Cadence Innovus)? I think there are no reg2reg timing paths at the top level.
Thanks,
Steve.
I have a digital block. I implemented it as a hard macro, and extracted the timing model .lib.
Then, I instantiated this block into a top module (the top module only has this macro, and I/O pads), and do PnR.
In the SDC file, I just set input and output delays associated with this hard macro.
My question is how to check its timing at the top level? and what types of timing should I check (in Cadence Innovus)? I think there are no reg2reg timing paths at the top level.
Thanks,
Steve.