Time borrowing is borrowing of time from a path with lesser delay to a path with greater delay. It is possible with latch based design as a latch is level triggered device unlike flip flops which are edge triggered.
For eg... say the clock period is 10 ns..
CL- Combinational Logic
CL 1 - takes 12 ns to compute the data;
CL2 - takes 5 ns to compute the data;
If we use latch ; we can share the extra 2 ns of CL 1 to CL 2; as the latch (negative enabled) is active for the entire positive phase of the clock signal.