timing analysis results from 3 different gate models: ccs,ecsm and nldm

[tangqin55]

I tried to used ccs, ecsm, and nldm .lib file to check the timing ISCAS 85 circuits, but I found the critical path delay and slew are same.
Is it practical?

What I did is like these:
step 1. use RTL compiler to synthesize the circuit using ccs.lib file, then I got the verilog netlist and timing report.

step 2. Since I want to use different gate models in the exact same circuit. I used the same verilog netlist and ecsm.lib file to elaborate and report timing without synthesize -to_generic -effort high
and synthesize -to_mapped -effort high -csa_effort high.

step 3. same as step2, but use nldm.lib

I didn't perform synthesize at step 2 and step 3 since it will optimize the design and some gate sizes probably will change.

 

[oratie]

Yes, it is practical. You may only see the difference on the post-routed design with extracted coupling capacitance. Simple netlist without extracted RC gives the same timing regardless of the kind of library.

 

[jeevan.life]

Yes, it is practical. You may only see the difference on the post-routed design with extracted coupling capacitance. Simple netlist without extracted RC gives the same timing regardless of the kind of library.

Exactly, try with a bit of routes, things change, ccs will be more accurate.

 

[tangqin55]

Yes, it is practical. You may only see the difference on the post-routed design with extracted coupling capacitance. Simple netlist without extracted RC gives the same timing regardless of the kind of library.

I didn't get it. different lib use different gate models.
Before P&R, the complier just estimate the load of every gate and calculate the gate delays.
then, the results by using different lib files should be different.....

Could you tell me the reason?

 

[jeevan.life]

I didn't get it. different lib use different gate models.
Before P&R, the complier just estimate the load of every gate and calculate the gate delays.
then, the results by using different lib files should be different.....

Could you tell me the reason?

Different .lib format stores the same slew and delay table. In case of ccs, the waveform is sampled more which means that there will be higher number of entries in the table and greater accuracy due to elimination of intrapolation and extrapolation. So in ideal case, the slew is constant or the same. So in your case may be its a value that is well in the .lib look up table. Try varying the slew at the input of a cell and try out

 

[tangqin55]

Different .lib format stores the same slew and delay table. In case of ccs, the waveform is sampled more which means that there will be higher number of entries in the table and greater accuracy due to elimination of intrapolation and extrapolation. So in ideal case, the slew is constant or the same. So in your case may be its a value that is well in the .lib look up table. Try varying the slew at the input of a cell and try out

This is the .sdc file (the circuit is combinational circuit, so there is no clock):
set_units -time ns -capacitance fF
set_max_delay 5 -from [all_inputs] -to [all_outputs]
set_load 20 [all_outputs]
set_input_transition 0.02 [all_inputs]

If I change the input slew, then the change is applied to all 3 steps (for ssc.lib, ecsm.lib and nldm.lib files).
So I tried different set_input_transition , the critical path delay and slew are still same for three .lib files.

 

[oratie]

I didn't get it. different lib use different gate models.
Before P&R, the complier just estimate the load of every gate and calculate the gate delays.
then, the results by using different lib files should be different.....

Could you tell me the reason?

If you look inside all of these .lib, you probably see the same (exactly the same) tables like

timing () {
related_pin : "A1";
timing_type : combinational;
cell_rise (delay_template_7x7_0) {
index_1 ("0.0022, 0.0068, 0.016, 0.0343, 0.071, 0.1443, 0.291");
index_2 ("0.00053, 0.00111, 0.00228, 0.00461, 0.00928, 0.0186, 0.03726");
values ( \
"0.01751, 0.01988, 0.02423, 0.03242, 0.0485, 0.08059, 0.1448", \
"0.01889, 0.02127, 0.02562, 0.0338, 0.04992, 0.08196, 0.1461", \


These LUT tables for pre-route delay calculations (as they are the same in all libs, you will get the same result). After routing and RC extracting (with coupling caps), the tool uses more accurate tables, that present in CCS and ECSM libs only.

 

[tangqin55]

If you look inside all of these .lib, you probably see the same (exactly the same) tables like

timing () {
related_pin : "A1";
timing_type : combinational;
cell_rise (delay_template_7x7_0) {
index_1 ("0.0022, 0.0068, 0.016, 0.0343, 0.071, 0.1443, 0.291");
index_2 ("0.00053, 0.00111, 0.00228, 0.00461, 0.00928, 0.0186, 0.03726");
values ( \
"0.01751, 0.01988, 0.02423, 0.03242, 0.0485, 0.08059, 0.1448", \
"0.01889, 0.02127, 0.02562, 0.0338, 0.04992, 0.08196, 0.1461", \


These LUT tables for pre-route delay calculations (as they are the same in all libs, you will get the same result). After routing and RC extracting (with coupling caps), the tool uses more accurate tables, that present in CCS and ECSM libs only.

I compare the ccs.lib and nldm.lb. the differences are :
1. ccs.lib has receiver capacitance lut, nldm doesn't.
2. ccs.lib has current lut, nldm doesn't.
They have exactly same cell_fall, cell_rise, fall_transition and rise_transition table.
Then I understand why the results from these different .lib files are same......

is my following understanding correct?

Before P&R, the simulator just estimate the gate load capacitance and different .lib files use the same delay and slew lut as nldm for roughly delay and
slew estimation.
However, if the routing and RC are extracted, ccs.lib will use current and calculated effective capacitance to calculate the output waveform for delay and slew calculation. While ecsm.lib uses voltage lut and calculated effective capacitance to calculate the delay and slew?

 

[jeevan.life]

I compare the ccs.lib and nldm.lb. the differences are :
1. ccs.lib has receiver capacitance lut, nldm doesn't.
2. ccs.lib has current lut, nldm doesn't.
They have exactly same cell_fall, cell_rise, fall_transition and rise_transition table.
Then I understand why the results from these different .lib files are same......

is my following understanding correct?

Before P&R, the simulator just estimate the gate load capacitance and different .lib files use the same delay and slew lut as nldm for roughly delay and
slew estimation.
However, if the routing and RC are extracted, ccs.lib will use current and calculated effective capacitance to calculate the output waveform for delay and slew calculation. While ecsm.lib uses voltage lut and calculated effective capacitance to calculate the delay and slew?

:grin: you got it right

 

[oratie]

Yes, you right. To see the bigger difference between NLDM and CCS, you need to extract RC with coupling caps (don't ground them).

 

[tangqin55]

Thanks Guys!!:razz:

For CCS model, when there are wire informations, the wire will be approximated by an effective capacitance (Ceff). It means the output waveform of every gate is
the voltage of Ceff driven by the current in ccs.lib. How to account for the coupling caps and resistive wires depends on the interconnect delay calculation method, which is not in the .lib file.
therefore, it seems that the accuracy of ccs highly depends on the ceff calculation method.

How did the simulator know when to use delay and slew lut in ccs.lib and when to use the current for delay calculation?
I didn't find any conditional option in the lib file.
may I force the complier to use current in ccs.lib file for delay and slew calculation?

 

[oratie]

Thanks Guys!!:razz:
How did the simulator know when to use delay and slew lut in ccs.lib and when to use the current for delay calculation?
I didn't find any conditional option in the lib file.
may I force the complier to use current in ccs.lib file for delay and slew calculation?

For Synopsys PrimeTime:

set rc_driver_model_mode advanced
set rc_receiver_model_mode advanced

 

[tangqin55]

For Synopsys PrimeTime:

set rc_driver_model_mode advanced
set rc_receiver_model_mode advanced

I added them to my .tcl script, but the results are same.

 

[oratie]

Please, read the manual for these app. variables. PrimeTime will start use CCS data only with RC parasitics (with coupling caps). Without RC, it will use NLDM LUTs regardless of these vars.

 

[tangqin55]

Please, read the manual for these app. variables. PrimeTime will start use CCS data only with RC parasitics (with coupling caps). Without RC, it will use NLDM LUTs regardless of these vars.

I've read <PrimeTime@ user guide advanced timing analysis> and <synthesis variables and attributes>.
Thanks a lot.

 

[tariq786]

Can someone explain what is

ccs, ecsm, and nldm .lib file ? and why are they needed?

 

[tangqin55]

Can someone explain what is

ccs, ecsm, and nldm .lib file ? and why are they needed?

ccs: current source model from synopsys
ecsm: effective current source model from cadence
nldm: nonlinear delay model
they are used for static timing analysis.

During timing analysis, the .lib or .db(Primetime) are needed. differen .lib or .db file use different gate delay models like ccs.