tangqin55
Member level 3
I tried to used ccs, ecsm, and nldm .lib file to check the timing ISCAS 85 circuits, but I found the critical path delay and slew are same.
Is it practical?
What I did is like these:
step 1. use RTL compiler to synthesize the circuit using ccs.lib file, then I got the verilog netlist and timing report.
step 2. Since I want to use different gate models in the exact same circuit. I used the same verilog netlist and ecsm.lib file to elaborate and report timing without synthesize -to_generic -effort high
and synthesize -to_mapped -effort high -csa_effort high.
step 3. same as step2, but use nldm.lib
I didn't perform synthesize at step 2 and step 3 since it will optimize the design and some gate sizes probably will change.
Is it practical?
What I did is like these:
step 1. use RTL compiler to synthesize the circuit using ccs.lib file, then I got the verilog netlist and timing report.
step 2. Since I want to use different gate models in the exact same circuit. I used the same verilog netlist and ecsm.lib file to elaborate and report timing without synthesize -to_generic -effort high
and synthesize -to_mapped -effort high -csa_effort high.
step 3. same as step2, but use nldm.lib
I didn't perform synthesize at step 2 and step 3 since it will optimize the design and some gate sizes probably will change.
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