Yes, it is practical. You may only see the difference on the post-routed design with extracted coupling capacitance. Simple netlist without extracted RC gives the same timing regardless of the kind of library.
Yes, it is practical. You may only see the difference on the post-routed design with extracted coupling capacitance. Simple netlist without extracted RC gives the same timing regardless of the kind of library.
I didn't get it. different lib use different gate models.
Before P&R, the complier just estimate the load of every gate and calculate the gate delays.
then, the results by using different lib files should be different.....
Could you tell me the reason?
Different .lib format stores the same slew and delay table. In case of ccs, the waveform is sampled more which means that there will be higher number of entries in the table and greater accuracy due to elimination of intrapolation and extrapolation. So in ideal case, the slew is constant or the same. So in your case may be its a value that is well in the .lib look up table. Try varying the slew at the input of a cell and try out
I didn't get it. different lib use different gate models.
Before P&R, the complier just estimate the load of every gate and calculate the gate delays.
then, the results by using different lib files should be different.....
Could you tell me the reason?
I compare the ccs.lib and nldm.lb. the differences are :If you look inside all of these .lib, you probably see the same (exactly the same) tables like
timing () {
related_pin : "A1";
timing_type : combinational;
cell_rise (delay_template_7x7_0) {
index_1 ("0.0022, 0.0068, 0.016, 0.0343, 0.071, 0.1443, 0.291");
index_2 ("0.00053, 0.00111, 0.00228, 0.00461, 0.00928, 0.0186, 0.03726");
values ( \
"0.01751, 0.01988, 0.02423, 0.03242, 0.0485, 0.08059, 0.1448", \
"0.01889, 0.02127, 0.02562, 0.0338, 0.04992, 0.08196, 0.1461", \
These LUT tables for pre-route delay calculations (as they are the same in all libs, you will get the same result). After routing and RC extracting (with coupling caps), the tool uses more accurate tables, that present in CCS and ECSM libs only.
I compare the ccs.lib and nldm.lb. the differences are :
1. ccs.lib has receiver capacitance lut, nldm doesn't.
2. ccs.lib has current lut, nldm doesn't.
They have exactly same cell_fall, cell_rise, fall_transition and rise_transition table.
Then I understand why the results from these different .lib files are same......
is my following understanding correct?
Before P&R, the simulator just estimate the gate load capacitance and different .lib files use the same delay and slew lut as nldm for roughly delay and
slew estimation.
However, if the routing and RC are extracted, ccs.lib will use current and calculated effective capacitance to calculate the output waveform for delay and slew calculation. While ecsm.lib uses voltage lut and calculated effective capacitance to calculate the delay and slew?
Thanks Guys!!:razz:
How did the simulator know when to use delay and slew lut in ccs.lib and when to use the current for delay calculation?
I didn't find any conditional option in the lib file.
may I force the complier to use current in ccs.lib file for delay and slew calculation?
For Synopsys PrimeTime:
set rc_driver_model_mode advanced
set rc_receiver_model_mode advanced
Please, read the manual for these app. variables. PrimeTime will start use CCS data only with RC parasitics (with coupling caps). Without RC, it will use NLDM LUTs regardless of these vars.
ccs: current source model from synopsysCan someone explain what is
ccs, ecsm, and nldm .lib file ? and why are they needed?
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