Startpoint: rst_n (input port)
Endpoint: v_data_array_reg[0]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
scale_8_5_gai ForQA cb35os142_max
Point Incr Path
-----------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
input external delay 0.00 0.00 r
rst_n (in) 0.00 0.00 r
U282/ZN (oai221d2) 158.42 158.42 f
U270/ZN (inv0d1) 4.99 163.41 r
v_data_array_reg[0]/ENN (denrq2) 0.93 164.34 r
data arrival time 164.34
clock clk (rise edge) 14.00 14.00
clock network delay (ideal) 0.00 14.00
clock uncertainty -0.50 13.50
v_data_array_reg[0]/CP (denrq2) 0.00 13.50 r
library setup time -0.63 12.87
data required time 12.87
-----------------------------------------------------------
data required time 12.87
data arrival time -164.34
-----------------------------------------------------------
slack (VIOLATED) -151.47
There is a warning during SYNTHESIS
Warning: Design 'scale_8_5_gai' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
The script about rst_n is :
set_drive 0 [get_ports rst_n]
remove_input_delay [get_ports rst_n]
set_dont_touch_network [get_ports rst_n]
what is the timeunit for the above representation of cell delay....if it is picoseconds...its fine ....otherwise u will have a problem....i dont think it will b ein nano seconds....
and waht about u r clock period .....
"clock clk (rise edge) 14.00 14.00"
from this i see that u r clock period is 14 ps...is it true ?
check this nformation properly...in which timeunit u r library has been characterized?
and also try to generate a timing report with report_timing -capacitance option so that u can see how much is the load capacitance on each of the net
u can add set_false_path -from [get_ports reset] (if it is really a false path)
one more thing which is confusing is u r clock period :
set CLK_PRD 10
create_clock -name clk -period $CLK_PRD [get_ports clk]
but in u r timing report....
clock clk (rise edge) 14.00 14.00
it shows that it is "14"
i think u should think about max transition time? Just think about it and change u r max transition time and u would be able to resolve u r violations.
Startpoint: rst_n (input port)
Endpoint: v_data_array_reg[0]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/Port Wire Load Model Library
------------------------------------------------
scale_8_5_gai ForQA cb35os142_max
Point Incr Path
-----------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
input external delay 0.00 0.00 r
rst_n (in) 0.00 0.00 r
U282/ZN (oai221d2) 158.42 158.42 f
U270/ZN (inv0d1) 4.99 163.41 r
v_data_array_reg[0]/ENN (denrq2) 0.93 164.34 r
data arrival time 164.34
clock clk (rise edge) 14.00 14.00
clock network delay (ideal) 0.00 14.00
clock uncertainty -0.50 13.50
v_data_array_reg[0]/CP (denrq2) 0.00 13.50 r
library setup time -0.63 12.87
data required time 12.87
-----------------------------------------------------------
data required time 12.87
data arrival time -164.34
-----------------------------------------------------------
slack (VIOLATED) -151.47
There is a warning during SYNTHESIS
Warning: Design 'scale_8_5_gai' contains 1 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134)
The script about rst_n is :
set_drive 0 [get_ports rst_n]
remove_input_delay [get_ports rst_n]
set_dont_touch_network [get_ports rst_n]
Ignore it during the synthesis, back-end will handle it for you. just about the reset tree balancing. If you don't want to see it in the synthesis, set ideal net or set load on it.
Hi, everyone,
I think the source is the high fanout net, so you should check the high fanout in the warning and deal with it. And the transition time is a little large, you may check it, usual, it's 0.1~0.5ns, but it's not fatal.
Maybe, there are synchronous DFF in ur design, and remove the "set drive 0 [input rst_n]".
BTW, Because the reset signal is not controlled by clock edge, u can ignore this violation.
according to ur timign report i observed that there is a huge load on the rst_n.since this is a reset for u r design u have to define an ideal net on the rst_n.it will sovle u r problem.