If the input pulse doesnt repeat and this is being fed as clock to the synchronous counter then the output of the counter will be stuck.
This is about exactly doubling the input pulse width. What you have mentioned is a clock divider circuit.
According to me the right way is to design a up/down counter. When the input pulse is '1' put the counter in up mode and when the pulse reverses put the counter in down mode. The output should be '1' for non zero values of the counter. So the input pulse will be doubled by the exact duration for which it was '1'.
Cheers,
eChipDesign.
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