The simplest way to design a pulse generator

[pennsia]

pulse generator spanish

Could anyone tell me the simplest way to design a pulse generator which will double the width of the input pulse by clocking it? The input pulse width has nothing to do with the clock pulse. Thanks a lot.

 

[Suresh_Patel]

Re: pulse generator

If your design permits, you can use micro controoler.
You have not specified the min/max value & frquency range of the pulse input.

 

[pennsia]

Re: pulse generator

It is an interview question. Assume the width of input pulse (let's say only one pulse) is between 4Tclk and 5Tclk (Tclk is the input clk cycle time) and it could start from any point (may align with the clk edge or not). But the output pulse width needs to be exact twice of the input pulse.

 

[saeed_pk]

pulse generator

if you want just a simple Digital Pulse
then use 4-bit or 8-bit Synchronous Counter
Feed you input pulse to CLOCK and derived o/p by D1
(second Least Significant Bit of the counter system will be doubling the width and halving the frequency.

 

[pennsia]

Re: pulse generator

Thanks saeed_pk for your reply. Could you give me a schematic? cause I'm still confusing...

 

[Suresh_Patel]

Re: pulse generator

Synchronous counter will give you (D1 o/p) half the i/p frequency having 50% duty cycle.
Input pulse width may have any duty cycle.

 

[eChipDesign]

If the input pulse doesnt repeat and this is being fed as clock to the synchronous counter then the output of the counter will be stuck.

This is about exactly doubling the input pulse width. What you have mentioned is a clock divider circuit.

According to me the right way is to design a up/down counter. When the input pulse is '1' put the counter in up mode and when the pulse reverses put the counter in down mode. The output should be '1' for non zero values of the counter. So the input pulse will be doubled by the exact duration for which it was '1'.

Cheers,
eChipDesign.

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eChip Design Labs
VLSI Training for Verilog and System Verilog
Nagercoil, TamilNadu

**broken link removed**

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[skyfaye]

If it's an interview question, then the answer is usually suppose to be quick and simple. So here's a typical pulse stretcher used in digital design.

// stretch din for fast_clk to catch
always @ (posedge fast_clk)
begin
if (rst) begin
din_d1 <= #1 1'b0;
din_strh <= #1 1'b0;
end
else begin
din_d1 <= #1 din;
din_strh <= #1 (din_d1 | din); // din will be exactly twice as wide
end
end

 

[eChipDesign]

The above code just increase the pulse by one 'fast clock' because you are just introducing a flop and 'or'ing with the signal.

It definitely doesnt double the pulse width. Would work for cases where the width of the pulse is one fast clock.

=====================================================
eChip Design Labs
VLSI Training for Verilog and System Verilog
Nagercoil, TamilNadu

**broken link removed**

=====================================================