The impaction of the CTS to the design

[crystalfish]

Hi
We all know that while using the SoCE to synthesis the clock tree, we have to deal with the *.ctstch file. This file specifies the three important parameters of the clock tree, the latency, the skew and the transition time. So my question is, how do these three impact the design?
As far as I know, the clock latency has certain effect on the running frequency of the system and the clock skew can cause the setup/hold time violation. Are these correct? And I don't konw the effect of the transition yet, can anybody tell me?

 

[chinnisunny]

ABOUT TRANSITION TIME.


Delay through a cell is often determined by the cell’s intrinsic delay, load that it is driving, and input transition (slew)
•Transition is the time it takes for the pin to change state
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In ASICs, the delay of a cell is affected by:

The input transition time (or slew rate)
The total load “seen” by the output transistors
Net capacitance and “downstream” pin capacitances
These will affect how quickly the input and output
transistors can “switch"

Greater is the value of clock transition time, greater is the setup time, slow transition means more time for the transistor(s) to turn off/on.