The gate of a PMOS is connected to the PAD by a very very long mental line

[NO1_NANO]

Hi everyone!

In my PLL design, the control voltage of the VCO works on the gate of a PMOS in the amplitude control circuit of the VCO.
In the layout design, the routing of the control voltage is very long,over 1080um, we use M6. And it has been pulled to a PAD so we can test it.
I think we must take the antenna effect into consideration, but how? Put a jump up mental near the gate? Or a diode?

Please help! Thank you!

 

[erikl]

by a very very long mental line
Put a jump up mental near the gate? Or a diode?

I think a diode near the PMOS would be the safest possibility. Could be integrated into the same nwell as the PMOS:
Given the long routing connection, the additional parasitic cap wouldn't matter.
____
BTW: I hope this isn't really a mental connection. Cause this works only in esoteric circuits ;-)

 

[NO1_NANO]

I think a diode near the PMOS would be the safest possibility. Could be integrated into the same nwell as the PMOS:
View attachment 88753 Given the long routing connection, the additional parasitic cap wouldn't matter.
____
BTW: I hope this isn't really a mental connection. Cause this works only in esoteric circuits ;-)

Thank you for your help!:smile:
And do you mean this is not a situation that can be solved by using a jump up mental? Because this method only works in a small number of circumstances? (That's my understanding of the word esoteric~)

- - - Updated - - -

Oh sorry, I just found I made a mistake, it is not a PMOS, it is a NMOS.

 

[erikl]

And do you mean this is not a situation that can be solved by using a jump up mental?

No, this doesn't help: After the next metal deposition/etch you'd get the same antenna violation problem.

Because this method only works in a small number of circumstances?

No: the diode method helps always. Metal jumping only if you know the production process and the meaning of antenna violation.

Metal jumping only helps, if the jumps all have short connections to the gate, and the long (top) metal connection to the pad at the end has a junction connection to silicon - this is only true if it is a real input and/or output pad with drivers, which is possibly not the case for a test pad (if it doesn't contain an ESD structure).

(That's my understanding of the word esoteric~)

No: I think you should use the correct word metal instead of mental. Mental means by intellectual (or spiritual) capability - and this doesn't create a real connection on silicon, I'd say!

it is not a PMOS, it is a NMOS.

Then use an n⁺p diode in substrate, next to the NMOS.

 

[NO1_NANO]

I got it! Thank you very much, and sorry for the wrong word.:grin: