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Dear, I am working on a layout of capacitor-based circuit. i have passed all LVs and DRC, but i have one error in ERC, as shown in the figure. This error shows that ntap is connected to GROUND. Could you suggest mehow to address this problem. i have crossed checked multple times my circuit it is fine.
I don't see a specific problem with a NWell being biased to vss, if
this is purposeful, like trying to get a P+ resistor in a quieter tub
or making a P+/Nw diode that wants its cathode to ground (like
many bandgaps in CMOS, although that structure really ends up
being a PNP).
Perhaps what you lack is a recognition layer which applies the
special exceptions like these cases.
Or perhaps you just screwed up and it should have been a ptap
to ground or a ntap to vdd all along. We don't know about that.
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