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The effect of vias on PCB traces.

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Olxx

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fpga and pcb and reflection and pdf

Could someone explain me the following in short:
I have a layout of my 4-layer PCB. The traces should carry relatively high-speed digital data (up to 80MHz) from onboard FPGA to the edge connectors. The trace's routing on the board is really dense so I have to put some vias in order to complete the routing successfully. Which "via" effect should I expect on 80MHz (TTL levels)?

Regards,
Olxx
 

flatulent

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pcb via inductance

The vias will act like approximately 100 pH inductors in series with your signals. This will have the effect of more time delay, longer rise and fall times. If you require the signals to arrive at the destination at the same time you should have the same line length and the same number of vias in each line. At your signalling speed this may not be a problem since at ten times the bitrate (the probable frequency of the rise and fall edges) the reactance is under 1 Ohm.
 

backdoor_

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effect of vias on pcb

80 MHz isn't all that high frequency to worry. The via inductance has a very small impact at 80 MHz.
What matters is the sharp rising and falling edge of your signal which produce the high frequency components.
1 ns of rising and falling edges can contain a pretty decent power level at even at 600 - 700 MHz.

cheers,
 

sigint

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effects vias pcb traces

The vias will add approximately 1 PF of capacitance to the trace length the switch of layers may also affect the impedance of the trace the via will produce a reflection which with ttl logic probably will not cause a problem.

SiGiNT
 

Olxx

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Thanks to you all. Now I am sure that everything should works fine.

Regards,
Olxx
 

arcnet

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It's not the clock frequency but the edge rate of your signals that you should be worried about in terms of signal integrity effects of vias. The via will have inductance, whose value will depend upon the loop the return current has to pass through to change layers. The via will also have
capacitance in the order of 0.5-1.0pf. If your edge rates are controllable, slow them to least you can get away with in your timing budget If not try and match the number of via's on synchronous signals, try to route on one layer. Decouple your design to provide adeqaute paths to minimise loop inductance.
 

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