cross talk guidlines for very low rise time PCB

[yefj]

Hello , I have a signal with risetime of 3ns which is BW=100Mhz which is not much of an RF challenge.
But I want to understand the principle and see at what cases it is starting to be a problem?
1A is the input of the inverter 1Y is the output.
These lines have distance between them.
"Some of the xtalk depends on risetime and some on coupling length."
Is there some wavelength criteria in dimentions so I could predict there would be cross talk problem?
Also signal integrity has a strong bond to resonance (haf wavelength structures)
I'll be glad to have some intuition on the subject.
Thanks.

https://assets.nexperia.com/documents/data-sheet/74ABT04.pdf

 

[D.A.(Tony)Stewart]

If you compute min. Track clearance for crosstalk in Saturn’s pcb program to something like 3 cm/pF of adjacent coupling you may be too close. This why interleaved or coplanar Gnd tracks are used, to reduce x-talk. Computing the Zc(f) for a given length with adjacent track impedance defined will tell you how much voltage of crosstalk exists based on total C, f , Z and length. You can estimate SNR from that. The same is true for trace inductance usually <10 nH/cm.

Now combining both parasitic LC if your Rs is not matched will give under damped oscillations. If nominal VOL / IOL = 350 mV / 20 mA =ZOL = 17.5 Ohms and you want to reduce ringing , add at least 22 to 33 ohms.