testbench signal monitor

[peen1]

In my testbench, I need to monitor a signal (wire/reg) buried deep in the design hierarchy. The hierarchy keeps on changing in different designs but the testbench remains the same. Is there any tool that can create an alias to the signal (alias created on signal declaration) and can automatically bring it to the testbench level?

 

[lostinxlation]

You can create a signal declaration file and run a perl(or whatever) script with it everytime you run the siml to replace the path variables in the testbench with the hierarchical paths from declaration file.