testbench output control, stupid question

[faust861]

testbench output control

Hi to all!
I have a quite stupid question, I think.
I have a testbench, where I force the output to the right result. If my code works how I expect, the output would be exactly equal to the one I expected, while if my code doesn't work, I will see red X on some parts or on all the output signal in ModelSim.

The stupid question is this: how could I do to have a std_logic signal which tells me the rightness of the output? I mean: for example a signal which is low when the output is right, high when the output goes to X

thank you

 

[rca]

the main issue, is when X appears during a simulation, this one is propagated, you should never used the X state, only to detect a unwanted behavior.

 

[faust861]

the main issue, is when X appears during a simulation, this one is propagated, you should never used the X state, only to detect a unwanted behavior.

sorry, maybe I wasn't too clear...

The X doesn't appear because my code is wrong, but because the output of the code is not the same of the output I force in testbench.
For example, here it's a part of my testbench:

cicla_Num_e_Den : process
	begin
	  t_Start_Div <= '0';
	  wait for (4.63 ns);
		t_Start_Div <= '1';
		wait for (4.63 ns);
		t_Start_Div <= '0';
		wait until (t_End_div_int = '1');
		t_Denominatore <= t_Denominatore + 1;
		[b]t_Quoziente <= (t_Numeratore) / ("000" & t_Denominatore);
  		t_Resto <= (t_Numeratore) rem (t_Denominatore);[/b]		
		if t_Denominatore = ones_den_int then
			t_Numeratore <= t_Numeratore +1;
		end if;
		if t_Numeratore = ones_num_int and t_Denominatore = ones_den_int then
			t_reset <= '1';
			wait for (4.63 ns);
		  t_reset <= '0';
		end if;
		
end process;

I force t_Quoziente and t_Resto to be that values (integer division and remainder).
If my code works well, in ModelSim I will see that values in green. If my code doesn't work well, I will see no value, but X (or better U) in red.
For example, my code gives Quoziente (ratio) 0 and Resto (remainder) 0 even if there is a situation like 0/0 or 5/0, while the testbench recognizes a situation of division by zero and so in modelsim I see a X.

My question is: I want to drive a std_logic signal that is low when everything is right, high when the result is different from the forced value. How can be done this?

 

[rca]

first of all, try to use english to create your signal name, it will be more readable by all designer, and more reused.

for division, you should control by a if condition, that an unwanted condition, that'not exist, and in the same way, you could add a signal to reflect this if statement.