Testbench for cordic algorithm

[Kosyas41]

Thanks,but what do you mean about all of the files in the simulation and source directories of the IP?
it should be cordd.vhd cordd_tb.vhd and what else?

 

[K-J]

Thanks,but what do you mean about all of the files in the simulation and source directories of the IP?
it should be cordd.vhd cordd_tb.vhd and what else?

One example of the warning message from Modelsim says...
** Warning: (vsim-3473) Component instance "nco_ii_0 : cordd_nco_ii_0" is not bound

What this means is in none of the source files did it find the entity/architecture for 'cordd_nco_ii_0'. Find that file and compile it with Modelsim. Repeat this process for each and every similar warning. Keep repeating this until there are no more similar warnings when you try to start the simulation. At that point, you've compiled all of the files needed for simulation and should be good to go.

Kevin

 

[ads-ee]

Thanks,but what do you mean about all of the files in the simulation and source directories of the IP?
it should be cordd.vhd cordd_tb.vhd and what else?

You're telling me that you really don't understand that you must compile all the files that are instantiated in each file until you reach a point where there aren't any instantiated sub-components in a file or those instantiated components are library components from Altera's simulation libraries?

Your original post of the untitled_folder.zip (untitled folder\cordic_sample_gener\testbench\cordic_sample_gener_tb\simulation) didn't have a cordd_tb.vhd or a cordd.vhd file but it does have a cordic_sample_gener_tb.vhd which instantiates a bunch of other entities like

	component cordic_sample_gener is
	component altera_avalon_clock_source is
	component altera_conduit_bfm is
	component altera_conduit_bfm_0002 is
	component altera_avalon_reset_source is

and these files are found in the following directory:
untitled folder\cordic_sample_gener\testbench\cordic_sample_gener_tb\simulation\submodules
which has the following files:

altera_avalon_clock_source.sv
altera_avalon_reset_source.sv
altera_conduit_bfm.sv
altera_conduit_bfm_0002.sv
cordic_sample_gener.vhd
cordic_sample_gener_nco_ii_0_tb.vhd
verbosity_pkg.sv

 

[Kosyas41]

Ok,now I trying to compile all submodules files with tb file, its mean that i compile altera_avalon_clock_source.sv
altera_avalon_reset_source.sv
altera_conduit_bfm.sv
altera_conduit_bfm_0002.sv
cordic_sample_gener.vhd
cordic_sample_gener_nco_ii_0_tb.vhd
verbosity_pkg.sv
cordic_sample_gener_tb.vhd
but i have some errors and I really dont understand what does it means

vlog -reportprogress 300 -work work {/home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/altera_avalon_clock_source.sv}
# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:55:09 on Apr 19,2016
# vlog -reportprogress 300 -work work /home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/altera_avalon_clock_source.sv 
# -- Compiling module altera_avalon_clock_source
# ** Error: /home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/altera_avalon_clock_source.sv(30): (vlog-13006) Could not find the package (verbosity_pkg).  Design read will continue, but expect a cascade of errors after this failure.  Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.
# End time: 13:55:09 on Apr 19,2016, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
vlog -reportprogress 300 -work work {/home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/altera_avalon_reset_source.sv}
# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:55:09 on Apr 19,2016
# vlog -reportprogress 300 -work work /home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/altera_avalon_reset_source.sv 
# -- Compiling module altera_avalon_reset_source
# ** Error: /home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/altera_avalon_reset_source.sv(34): (vlog-13006) Could not find the package (verbosity_pkg).  Design read will continue, but expect a cascade of errors after this failure.  Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.
# End time: 13:55:09 on Apr 19,2016, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
vlog -reportprogress 300 -work work {/home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/altera_conduit_bfm.sv}
# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:55:09 on Apr 19,2016
# vlog -reportprogress 300 -work work /home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/altera_conduit_bfm.sv 
# -- Compiling module altera_conduit_bfm
# ** Error: /home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/altera_conduit_bfm.sv(56): (vlog-13006) Could not find the package (verbosity_pkg).  Design read will continue, but expect a cascade of errors after this failure.  Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.
# End time: 13:55:09 on Apr 19,2016, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
vlog -reportprogress 300 -work work {/home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/altera_conduit_bfm_0002.sv}
# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:55:09 on Apr 19,2016
# vlog -reportprogress 300 -work work /home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/altera_conduit_bfm_0002.sv 
# -- Compiling module altera_conduit_bfm_0002
# ** Error: /home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/altera_conduit_bfm_0002.sv(56): (vlog-13006) Could not find the package (verbosity_pkg).  Design read will continue, but expect a cascade of errors after this failure.  Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.
# End time: 13:55:09 on Apr 19,2016, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
vlog -reportprogress 300 -work work {/home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/verbosity_pkg.sv}
# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:55:09 on Apr 19,2016
# vlog -reportprogress 300 -work work /home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/verbosity_pkg.sv 
# -- Compiling package verbosity_pkg
# 
# Top level modules:
# 	--none--
# End time: 13:55:09 on Apr 19,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vcom -reportprogress 300 -work work {/home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/cordic_sample_gener.vhd}
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:55:10 on Apr 19,2016
# vcom -reportprogress 300 -work work /home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/cordic_sample_gener.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity cordic_sample_gener
# -- Compiling architecture rtl of cordic_sample_gener
# End time: 13:55:10 on Apr 19,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vcom -reportprogress 300 -work work {/home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/cordic_sample_gener_tb.vhd}
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 13:55:10 on Apr 19,2016
# vcom -reportprogress 300 -work work /home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/cordic_sample_gener_tb.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity cordic_sample_gener_tb
# -- Compiling architecture rtl of cordic_sample_gener_tb
# End time: 13:55:10 on Apr 19,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

 

[K-J]

Ok,now I trying to compile all submodules files with tb file, its mean that i compile altera_avalon_clock_source.sv
altera_avalon_reset_source.sv
altera_conduit_bfm.sv
altera_conduit_bfm_0002.sv
cordic_sample_gener.vhd
cordic_sample_gener_nco_ii_0_tb.vhd
verbosity_pkg.sv
cordic_sample_gener_tb.vhd
but i have some errors and I really dont understand what does it means

Seems pretty clear to me
Error: /home/kostya/Desktop/untitled folder/cordic_sample_gener/testbench/cordic_sample_gener_tb/simulation/altera_conduit_bfm_0002.sv(56): (vlog-13006) Could not find the package (verbosity_pkg).
I'm assuming that this package is defined in the file verbosity_pkg.sv which was the last file that was compiled...which means that the package was not available at the time that file altera_conduit_bfm_0002.sv was compiled.

In the Modelsim GUI, right click on any file and select 'Compile->Compile Order' and then select the 'Auto Generate' button. Then the files will be re-ordered so that they compile in the proper order.

Kevin Jennings

 

[Kosyas41]

Thanks for advice,but now I have a different errors, I think im also should add nco_ii_0 library but I cant find it((

vsim -L altera -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive work.cordic_generator_tb
# vsim 
# Start time: 02:28:07 on Apr 19,2016
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.cordic_generator_tb(rtl)
# Loading work.cordic_generator(rtl)
# Loading work.cordic_generator_nco_ii_0
# Loading altera_mf_ver.altshift_taps
# Loading lpm_ver.lpm_add_sub
# Loading lpm_ver.lpm_counter
# Loading sgate_ver.oper_add
# Loading sgate_ver.oper_mux
# Loading sv_std.std
# Loading work.verbosity_pkg
# Loading work.altera_avalon_clock_source
# Loading work.altera_conduit_bfm
# Loading work.altera_conduit_bfm_0002
# Loading work.altera_avalon_reset_source
# ** Warning: (vsim-3017) /home/kostya/bladeRF/hdl/quartus/cordic_generator/testbench/cordic_generator_tb/simulation/cordic_generator_nco_ii_0.vo(12986): [TFMPC] - Too few port connections. Expected 15, found 14.
#         Region: /cordic_generator_tb/cordic_generator_inst/nco_ii_0/nlOOl
# ** Warning: (vsim-3722) /home/kostya/bladeRF/hdl/quartus/cordic_generator/testbench/cordic_generator_tb/simulation/cordic_generator_nco_ii_0.vo(12986): [TFMPC] - Missing connection for port 'eq'.
# ** Warning: (vsim-3934) /home/kostya/bladeRF/hdl/quartus/cordic_generator/testbench/cordic_generator_tb/simulation/cordic_generator_tb.vhd(102): [TFMPC] - Missing VHDL connection for formal Verilog port 'reset_n'.
#         Region: /cordic_generator_tb/cordic_generator_inst_in_bfm
# ** Error: (vsim-3059) Cannot connect a VHDL array signal to Verilog scalar port 'sig_clken'.
#         Region: /cordic_generator_tb/cordic_generator_inst_in_bfm
# ** Warning: (vsim-3934) /home/kostya/bladeRF/hdl/quartus/cordic_generator/testbench/cordic_generator_tb/simulation/cordic_generator_tb.vhd(111): [TFMPC] - Missing VHDL connection for formal Verilog port 'reset_n'.
#         Region: /cordic_generator_tb/cordic_generator_inst_out_bfm
# ** Error: (vsim-3059) Cannot connect a VHDL array signal to Verilog scalar port 'sig_out_valid'.
#         Region: /cordic_generator_tb/cordic_generator_inst_out_bfm
# Error loading design

 

[ads-ee]

All of the warnings and errors are due to mismatches between the ports on various modules.

Either the files have been modified prior to attempting to run a simulation on the core (bad idea not baselining the simulation first) or there are extra files in the directory that you should NOT compile (I noticed some files seem to have similar names with numbers appended).

It seems like you expect us to read each error/warning to you. Try reading them youself, all of the ones you've had so far were self explanatory and once again so are these.

 

[Kosyas41]

Could you pls tell me which files I should not compile?You think that this files are similar .altera_conduit_bfm and altera_conduit_bfm_0002.or others?All of this files generated automatically from IP tool

 

[ads-ee]

Look in the file:
cordic_sample_gener\testbench\cordic_sample_gener_tb\simulation\submodules\altera_conduit_bfm_0002.sv

looking at the module port declaration (typical antiquated/obsolete syntax):

module altera_conduit_bfm_0002
(
   clk,
   reset,
   reset_n,
   sig_fsin_o,
   sig_out_valid
);

You'll notice there is a reset_n, which is used in the code....but the instance where this module is used in....
cordic_sample_gener\testbench\cordic_sample_gener_tb\simulation\cordic_sample_gener_tb.vhd

	cordic_sample_gener_inst_out_bfm : component altera_conduit_bfm_0002
		port map (
			clk              => cordic_sample_gener_inst_clk_bfm_clk_clk,               --     clk.clk
			reset            => cordic_sample_gener_inst_rst_bfm_reset_reset_ports_inv, --   reset.reset
			sig_fsin_o       => cordic_sample_gener_inst_out_fsin_o,                    -- conduit.fsin_o
			sig_out_valid(0) => cordic_sample_gener_inst_out_out_valid                  --        .out_valid
		);

Is missing the reset_n, so either the file has been changed or the IP testbench was written wrong or is the wrong version. Typical "quality" Altera IP.

 

[Kosyas41]

Thanks a lot)Im using the same software version,and I think not changed.

I found the same story in altera_conduit_bfm module testbench, where reset_n not mentioned.Its mean that I should check all modules in tb file and add signals which not mentioned, for example
reset_n => cordic_sample_gener_inst_reset_n
Am i right or not?And mb better to write tb by myself?

 

[ads-ee]

The problem is the signal is used in the submodule, so it may require a specific timing relationship to the other reset, or maybe none at all.

You could edit it and add the signal and just connect it to the inverted version of the other reset that already exists unless there is already a ....reset_n in the code that wasn't connected.

I'm not at all impressed by the quality of this testbench the tools supplied.