Testbench for cordic algorithm

[Kosyas41]

Hello,
Could you pls helm me with cordic VHDL testbench for this code/Im generated this code using IP core parameters

 

[K-J]

What specifically are you having trouble with that you need help?

Kevin

 

[ads-ee]

Did you even look through the directories produced by the IP tool?

untitled folder.zip\untitled folder\cordic_sample_gener\testbench\cordic_sample_gener_tb\simulation

This directory has a testbench for the IP. Perhaps you should try running that first. Or maybe you should read the IP's documentation, e.g. the user guide.

 

[Kosyas41]

yes i read IP documentations and simulate this tb from QSYS/ i do Generate-generate test bench system.so after this i go to this directory as you already mentioned/but i want to get waveform as shows in IP documentation/I open modelsim and compile cordic_sample_gener_tb.vhd which located on simulation folder.but i didnt get any timing diagrams/whats wrong

 

[ads-ee]

Did you add the signals to the waveform window...add wave *?

Did you get any errors in the transcript window?

Have you posted the transcript window so someone can look to see if there is a warning/error?
Oh, wait you didn't supply that information...I see the problem now...

 

[Kosyas41]

sorry.Now i upload pictures of my modelsim window,first i compile this project in quartus,after succesful compilation i run Tools/Run Simulation Tool/RTL simulation.after this i choose Compile and compile cordic_sample_gener_tb.vhd,then add all signals in object window,than press run all/but simulation didt started,i pressed run but all the signals are in red color

 

[ads-ee]

sorry.Now i upload pictures of my modelsim window,first i compile this project in quartus,after succesful compilation i run Tools/Run Simulation Tool/RTL simulation.after this i choose Compile and compile cordic_sample_gener_tb.vhd,then add all signals in object window,than press run all/but simulation didt started,i pressed run but all the signals are in red colorView attachment 128064View attachment 128065

Well you don't even have a clock, you'll need to put up the signals in the file

cordic_sample_gener_inst_clk_bfm : component altera_avalon_clock_source
		generic map (
			CLOCK_RATE => 50000000,
			CLOCK_UNIT => 1
		)
		port map (
			clk => cordic_sample_gener_inst_clk_bfm_clk_clk  -- clk.clk
		);

and see why the clock isn't being generated from this component. Perhaps the timescale of the simulator is wrong, sometimes these vendor clock components require 1ps resolution for simulation if you want them to work.

Does the project tab show that all the files are compiled that there aren't any missing files? Did you clean the simulation directory? If you have an old file and recompile but are missing that file from the design compilation (missing from project) then the old compiled version that still exists in the modelsim work directory will be used. I ususally write scripts to perform my simulations and avoid using the GUI to manage my compilation/simulation.

 

[Kosyas41]

When i generated testbench i have one warning/mb this is problem?



and what do you mean about "you don't even have a clock" I should put some code which describe the initial status of my signals?

 

[ads-ee]

and what do you mean about "you don't even have a clock" I should put some code which describe the initial status of my signals?

The clock shown in the waveform display in post #7 (the first signal in the list) shows U which means it's undriven between 1.350 ns and 2.350 ns. So either the module doesn't immediately drive the clock at time 0 ns and you therefore haven't run your simulation long enough or it's never driven. Try running the simulation for 100 ns or more (up to maybe 1us) and see if the clock shows up.

The warning is because you are specifying a clock frequency that is not obtainable. I don't know what IP that is so I can't comment on what is the minimum frequency allowed. I think you should read the documentation for each design element you are using. This isn't like an iPhone where you can just pick it up and use it.

 

[Kosyas41]

Thanks a lot/but I think the main problem is that.I didn't driven any of signals/because I trying to run for very long time and I didn't see any changes.

 

[ads-ee]

If you are running the testbench provided by the tool then you shouldn't have to drive any signals, the testbench should already be doing that.

 

[Kosyas41]

yes Im using this tool,and i hope that i should just simulate this tb and check how its work/but now I dont have any result((I want to be sure that cordic algorithm work properly

 

[ads-ee]

Hence one of my earlier posts...

1. delete the entire simulation work directory
2. use vlib work and recreate it
3. compile the design look for warnings/errors
4. post all warnings/errors from compilation if you still have a problem (use code tags and cut-paste from the transcript window, please don't post graphics of your screen), or alternatively just post the entire transcript window from the step 3 to the end of the compilation and run 100 ns command.

 

[Kosyas41]

thanks.i will try it tomorrow and will share with you my results

 

[Kosyas41]

Hi,i still have the same problem.First of all I will describe my steps.
1st i open IP catalog-DSP-Signal Generator-NCO,after this I create new IP variation,where i choose Genration algoritm Cordic with single output and after this Generate HDL
2nd Open Generate button and choose Generate Testbench system
3rd Create New project in Quartus and Run simulation.I have the following warnings

Warning (12188): OpenCore Plus Hardware Evaluation feature is turned on for the following cores
Warning (12190): "NCO Compiler" will use the OpenCore Plus Hardware Evaluation feature
Warning (265072): Messages from megafunction that supports OpenCore Plus feature
Warning (265073): Messages from megafunction that supports OpenCore Plus feature NCO MegaCore
Warning (265074): The output signals fsin_o and fcos_o are forced low when the evaluation time expires
Warning (265069): Megafunction that supports OpenCore Plus feature will stop functioning in 1 hour after device is programmed
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Warning (332060): Node: clk was determined to be a clock but was found without an associated clock assignment.
	Info (13166): Register cord_gen_nco_ii_0:nco_ii_0|asj_dxx:ux002|altshift_taps:dxxpdo_rtl_0|shift_taps_v5n:auto_generated|altsyncram_c2b1:altsyncram2|ram_block5a1 is being clocked by clk
Warning (210042): Can't convert time-limited SOF into POF, HEX File, TTF, or RBF
Warning (332060): Node: clk was determined to be a clock but was found without an associated clock assignment.
	Info (13166): Register cord_gen_nco_ii_0:nco_ii_0|cord_2c:cordinv|cordic_y_res_2c[1] is being clocked by clk
Warning (332060): Node: clk was determined to be a clock but was found without an associated clock assignment.
	Info (13166): Register cord_gen_nco_ii_0:nco_ii_0|cord_2c:cordinv|cordic_y_res_2c[1] is being clocked by clk
Warning (332060): Node: clk was determined to be a clock but was found without an associated clock assignment.
	Info (13166): Register cord_gen_nco_ii_0:nco_ii_0|cord_2c:cordinv|cordic_y_res_2c[1] is being clocked by clk

4th after this I go to Tools-Run simulation Tool-RTL Simulation
5th go to Compile-compile and choose tb file which was generated
6th Choose tb library and add all signals in to wave,after simulate run all,but simuation didnt started/
Could you pls guided me in right directon,because i tried all your advices but its not help((

 

[ads-ee]

Those warnings are not modelsim warnings, they are all from Quartus, how is that supposed to help anyone debug your simulation problem.

You need to post the Modelsim transcript window for the entire compilation (for simulation) and the run. We need to see if there are any issues there. You also don't describe what "but simuation didnt started" means. How am I supposed to know what doesn't start mean? Does it mean that the time in the simulator never goes past 0, does it mean the simulation runs but doesn't generate any waveforms (green,red, or blue lines), does it crash back to the OS, does it run with just U or X in the waveform (like before), does it generate waveforms but not what you expect...

You also disregarded post #7 where I told you to check the following component "altera_avalon_clock_source", by putting the signals in that component in the wave window and using the commands "restart -f; run 100 ns". If there isn't a clock being generated then your simulation will not run correctly. You also failed to define how long the simulation ran using RUN -ALL, if it only ran for 2.350 ns then, you haven't tried to make the simulation run further by typing the command "RUN 100 ns" or more, which I suggested in post #9.

You need to read this, It might help you learn to formulate questions that can be answered without requests for details. You also need to learn how to debug stuff, which takes a systematic and logical approach to isolating a problem...a skill which all good engineers have or develop.

 

[Kosyas41]

Hello,
Sorry for wrong explanations
So here I explain my modelsim warnings,after project simulation in Quartus I choose RTL simulation and open modelsim
1st I pressed Compile-compile and choose my tb file
2nd Simulate-start simulations and choose work library for tb file,should i add more libraries ?

vcom -reportprogress 300 -work work /home/kostya/Desktop/fff/cordd/testbench/cordd_tb/simulation/cordd_tb.vhd
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 14:37:13 on Apr 18,2016
# vcom -reportprogress 300 -work work /home/kostya/Desktop/fff/cordd/testbench/cordd_tb/simulation/cordd_tb.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity cordd_tb
# -- Compiling architecture rtl of cordd_tb
# End time: 14:37:13 on Apr 18,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vsim -do corddic_run_msim_rtl_vhdl.do -i -l msim_transcript work.cordd_tb
# vsim -i -l msim_transcript -do "corddic_run_msim_rtl_vhdl.do" 
# Start time: 14:37:26 on Apr 18,2016
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.cordd_tb(rtl)
# ** Warning: (vsim-3473) Component instance "cordd_inst : cordd" is not bound.
#    Time: 0 ps  Iteration: 0  Instance: /cordd_tb File: /home/kostya/Desktop/fff/cordd/testbench/cordd_tb/simulation/cordd_tb.vhd
# ** Warning: (vsim-3473) Component instance "cordd_inst_clk_bfm : altera_avalon_clock_source" is not bound.
#    Time: 0 ps  Iteration: 0  Instance: /cordd_tb File: /home/kostya/Desktop/fff/cordd/testbench/cordd_tb/simulation/cordd_tb.vhd
# ** Warning: (vsim-3473) Component instance "cordd_inst_in_bfm : altera_conduit_bfm" is not bound.
#    Time: 0 ps  Iteration: 0  Instance: /cordd_tb File: /home/kostya/Desktop/fff/cordd/testbench/cordd_tb/simulation/cordd_tb.vhd
# ** Warning: (vsim-3473) Component instance "cordd_inst_out_bfm : altera_conduit_bfm_0002" is not bound.
#    Time: 0 ps  Iteration: 0  Instance: /cordd_tb File: /home/kostya/Desktop/fff/cordd/testbench/cordd_tb/simulation/cordd_tb.vhd
# ** Warning: (vsim-3473) Component instance "cordd_inst_rst_bfm : altera_avalon_reset_source" is not bound.
#    Time: 0 ps  Iteration: 0  Instance: /cordd_tb File: /home/kostya/Desktop/fff/cordd/testbench/cordd_tb/simulation/cordd_tb.vhd
# do corddic_run_msim_rtl_vhdl.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim LE vmap 10.3d Lib Mapping Utility 2014.10 Oct  7 2014
# vmap -modelsim_quiet work rtl_work 
# Modifying /home/kostya/altera/15.0/modelsim_ase/linuxaloem/modelsim.ini
# 
# vlib cordd
# ** Warning: (vlib-34) Library already exists at "cordd".
# vmap cordd cordd
# Model Technology ModelSim LE vmap 10.3d Lib Mapping Utility 2014.10 Oct  7 2014
# vmap -modelsim_quiet cordd cordd 
# Modifying /home/kostya/altera/15.0/modelsim_ase/linuxaloem/modelsim.ini
# vlog -vlog01compat -work cordd +incdir+/home/kostya/Desktop/fff/cordd/synthesis/submodules {/home/kostya/Desktop/fff/cordd/synthesis/submodules/cordd_nco_ii_0.v}
# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 14:37:29 on Apr 18,2016
# vlog -reportprogress 300 -vlog01compat -work cordd "+incdir+/home/kostya/Desktop/fff/cordd/synthesis/submodules" /home/kostya/Desktop/fff/cordd/synthesis/submodules/cordd_nco_ii_0.v 
# -- Compiling module cordd_nco_ii_0
# 
# Top level modules:
# 	cordd_nco_ii_0
# End time: 14:37:29 on Apr 18,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work cordd {/home/kostya/Desktop/fff/cordd/synthesis/cordd.vhd}
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 14:37:29 on Apr 18,2016
# vcom -reportprogress 300 -93 -work cordd /home/kostya/Desktop/fff/cordd/synthesis/cordd.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity cordd
# -- Compiling architecture rtl of cordd
# End time: 14:37:29 on Apr 18,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0

3rd after this I add all signals to wave and press run all.As you recommended my Run for 100 ns,all signals are red with U messages.but when Im trying to Run All nothing happens its mean that no changes in wave forms and time dont start counting its always 0 and delta 1. You also said that i should check "altera_avalon_clock_source" this component generated automatically from the tool and you said that i shouldt change something?

 

[K-J]

The file cordd.vhd was not compiled in Modelsim, only cordd_tb.vhd

Kevin Jennings

 

[Kosyas41]

The same problem when I compiled with both files

vcom -reportprogress 300 -work work /home/kostya/Desktop/fff/cordd/synthesis/cordd.vhd
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 15:36:36 on Apr 18,2016
# vcom -reportprogress 300 -work work /home/kostya/Desktop/fff/cordd/synthesis/cordd.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity cordd
# -- Compiling architecture rtl of cordd
# End time: 15:36:36 on Apr 18,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vcom -reportprogress 300 -work work /home/kostya/Desktop/fff/cordd/synthesis/cordd_tb.vhd
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 15:36:36 on Apr 18,2016
# vcom -reportprogress 300 -work work /home/kostya/Desktop/fff/cordd/synthesis/cordd_tb.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity cordd_tb
# -- Compiling architecture rtl of cordd_tb
# End time: 15:36:36 on Apr 18,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
vsim -do corddic_run_msim_rtl_vhdl.do -i -l msim_transcript work.cordd work.cordd_tb
# vsim -i -l msim_transcript -do "corddic_run_msim_rtl_vhdl.do" 
# Start time: 15:36:49 on Apr 18,2016
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.cordd(rtl)
# Loading work.cordd_tb(rtl)
# ** Warning: (vsim-3473) Component instance "nco_ii_0 : cordd_nco_ii_0" is not bound.
#    Time: 0 ps  Iteration: 0  Instance: /cordd File: /home/kostya/Desktop/fff/cordd/synthesis/cordd.vhd
# ** Warning: (vsim-3473) Component instance "nco_ii_0 : cordd_nco_ii_0" is not bound.
#    Time: 0 ps  Iteration: 0  Instance: /cordd_tb/cordd_inst File: /home/kostya/Desktop/fff/cordd/synthesis/cordd.vhd
# ** Warning: (vsim-3473) Component instance "cordd_inst_clk_bfm : altera_avalon_clock_source" is not bound.
#    Time: 0 ps  Iteration: 0  Instance: /cordd_tb File: /home/kostya/Desktop/fff/cordd/synthesis/cordd_tb.vhd
# ** Warning: (vsim-3473) Component instance "cordd_inst_in_bfm : altera_conduit_bfm" is not bound.
#    Time: 0 ps  Iteration: 0  Instance: /cordd_tb File: /home/kostya/Desktop/fff/cordd/synthesis/cordd_tb.vhd
# ** Warning: (vsim-3473) Component instance "cordd_inst_out_bfm : altera_conduit_bfm_0002" is not bound.
#    Time: 0 ps  Iteration: 0  Instance: /cordd_tb File: /home/kostya/Desktop/fff/cordd/synthesis/cordd_tb.vhd
# ** Warning: (vsim-3473) Component instance "cordd_inst_rst_bfm : altera_avalon_reset_source" is not bound.
#    Time: 0 ps  Iteration: 0  Instance: /cordd_tb File: /home/kostya/Desktop/fff/cordd/synthesis/cordd_tb.vhd
# ** Warning: (vsim-8684) No drivers exist on out port /cordd_tb/cordd_inst/fsin_o, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /cordd_tb/cordd_inst_out_fsin_o.
# ** Warning: (vsim-8684) No drivers exist on out port /cordd_tb/cordd_inst/out_valid, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /cordd_tb/cordd_inst_out_out_valid.
# do corddic_run_msim_rtl_vhdl.do
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Model Technology ModelSim LE vmap 10.3d Lib Mapping Utility 2014.10 Oct  7 2014
# vmap -modelsim_quiet work rtl_work 
# Modifying /home/kostya/altera/15.0/modelsim_ase/linuxaloem/modelsim.ini
# 
# vlib cordd
# ** Warning: (vlib-34) Library already exists at "cordd".
# vmap cordd cordd
# Model Technology ModelSim LE vmap 10.3d Lib Mapping Utility 2014.10 Oct  7 2014
# vmap -modelsim_quiet cordd cordd 
# Modifying /home/kostya/altera/15.0/modelsim_ase/linuxaloem/modelsim.ini
# vlog -vlog01compat -work cordd +incdir+/home/kostya/Desktop/fff/cordd/synthesis/submodules {/home/kostya/Desktop/fff/cordd/synthesis/submodules/cordd_nco_ii_0.v}
# Model Technology ModelSim ALTERA vlog 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 15:36:52 on Apr 18,2016
# vlog -reportprogress 300 -vlog01compat -work cordd "+incdir+/home/kostya/Desktop/fff/cordd/synthesis/submodules" /home/kostya/Desktop/fff/cordd/synthesis/submodules/cordd_nco_ii_0.v 
# -- Compiling module cordd_nco_ii_0
# 
# Top level modules:
# 	cordd_nco_ii_0
# End time: 15:36:52 on Apr 18,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# vcom -93 -work cordd {/home/kostya/Desktop/fff/cordd/synthesis/cordd.vhd}
# Model Technology ModelSim ALTERA vcom 10.3d Compiler 2014.10 Oct  7 2014
# Start time: 15:36:52 on Apr 18,2016
# vcom -reportprogress 300 -93 -work cordd /home/kostya/Desktop/fff/cordd/synthesis/cordd.vhd 
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity cordd
# -- Compiling architecture rtl of cordd
# End time: 15:36:52 on Apr 18,2016, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# 
add wave sim:/cordd/*
add wave sim:/cordd_tb/*
run -all
run
run
run
run

 

[ads-ee]

You need to compile all of the files in the simulation and source directories of the IP. In the best case scenario there should be absolutely NO warnings or errors reported by modelsim.

Once you've gotten rid of all the 'is not bound' warnings. If you have any other warnings post them for further help.

- - - Updated - - -

You could have saved a lot of time if you had posted this like I asked back in post #5. If you don't understand what is being asked, don't answer a different question or ignore the question. Ask for clarification about what they need to help you.

Remember forum members are not psychic we can't read your mind nor see anything through your eyes.