Hi all
I wrote a vhdl code for file read. Its for getting array of integers from the file.To check whether this program working properly ,Ineed to write a testbench.Please help t write testbench for this code. I am using xilinx 10.1 version.I generated atestbench in this , but couldn't work out.
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library ieee ;
use ieee .std_logic_1164 .all ;
USE ieee .std_logic_arith.all ;
use ieee .numeric_std .all ;
library std;
use std.textio .all ;
--use work.txt_util.all;
entity lciread is
port (
CLK : in std_logic ;
-- RST : in std_logic;
Y : out std_logic_vector ( 7 downto 0 ) ;
EOG : out std_logic
) ;
end lciread;
architecture read_from_file of lciread is
begin
process ( clk)
file infile : TEXT ;
variable fstatus : file_open_status;
variable l : line ;
variable temp: integer ;
constant prec: integer := 8 ;
begin
y<= ( others => '0 ') ;
--while reset = '1' loop
file_open( fstatus, infile, "myfile.txt" ,READ_MODE) ;
while ( not endfile ( infile) ) loop
if ( clk= '1 ' and clk'event ) then
readline ( infile, l) ;
read ( l ,temp) ;
y<= CONV_STD_LOGIC_VECTOR( temp,prec) ;
end if ;
end loop ;
file_close ( infile) ;
--end loop;
EOG <= '1 ';
end process ;
end read_from_file;
Last edited by a moderator: Aug 14, 2012