Tajira
Newbie level 5
Hi,
I am given a systemverilog design. My task is to optimize (reduce) the size of the design in terms of FPGA synthesis, and I need to increase the speed of Design. The target FPGA is Xilinx Artix and IDE is Vivado.
I want to know:
1) What may be the programming approaches i.e. what things I can make
right in order to achieve higher speeds and smaller sizes (Just general
guidelines).
2) What options in Vivado are available to achieve the same.
All answers, links, and guides are warmly welcome.
Looking forward to hearing from the experienced guys.
Best regards
Cheeku
I am given a systemverilog design. My task is to optimize (reduce) the size of the design in terms of FPGA synthesis, and I need to increase the speed of Design. The target FPGA is Xilinx Artix and IDE is Vivado.
I want to know:
1) What may be the programming approaches i.e. what things I can make
right in order to achieve higher speeds and smaller sizes (Just general
guidelines).
2) What options in Vivado are available to achieve the same.
All answers, links, and guides are warmly welcome.
Looking forward to hearing from the experienced guys.
Best regards
Cheeku