SystemVerilog : Optimizing code for speed and synthesis size

[Tajira]

Hi,
I am given a systemverilog design. My task is to optimize (reduce) the size of the design in terms of FPGA synthesis, and I need to increase the speed of Design. The target FPGA is Xilinx Artix and IDE is Vivado.

I want to know:
1) What may be the programming approaches i.e. what things I can make
right in order to achieve higher speeds and smaller sizes (Just general
guidelines).
2) What options in Vivado are available to achieve the same.


All answers, links, and guides are warmly welcome.

Looking forward to hearing from the experienced guys.

Best regards

Cheeku

 

[dpaul]

I can give you one advice on the task sequence. First try to address the max speed issue and then look for ways to reduce resource usage.

 

[TrickyDicky]

Reducing logic and improving speed are more a design problem that a specific SV problem.
Logic reduction is about assessing if a specific function really needs to do what it does.
Speed improvement comes from reducing the logic levels between registers.

Improving both speed and resource usage can sometimes be mutually exclusive. Adding pipelining usually adds more resources.

Its a very general question with very general answers. If you had more specific questions maybe we could help more.