Systemverilog interview question

[Basu_Gouda]

Taking clock as the reference how do you break 32 bit data into four 8 bit data using systemverilog

 

[RAJAT AGGARWAAL]

You yourself answered ,,,,using clock
but in which situation you are ,,we must have to know to suggest?

 

[permute]

I suspect they are looking for you to create a state machine that takes a 32b sample every 4 cycles, and outputs 1 8b segment per cycle.
this can be done using a mux and a counter. there are several ways to write a mux and counter.

VHDL allows signals/variables to be used in slicing, eg x(8*(sel+1)-1 downto 8*sel) is valid and efficient in VHDL. Verilog doesn't allow this -- it doesn't allow regs/wires to be used for slicing. Verilog would need an intermediate [7:0] wire [3:0] to be declared, and a generate statement to assign the elements -- Verilog does allow constants, params, and genvar's to be used in slicing. Verilog also has a nice [offset+:width] operator, which can be used instead of the standard [width+offset-1ffset]. I'm not sure if system verilog changes the behavior of [:] to allow regs/logics/wires to be used.

likewise, for 4 elements you can write out each element. The code isn't as reusable and you likely won't impress the interviewer with your knowledge of the language. At the same time its easier to get correct and you will at least seem competent enough to write basic HDL.