SystemC , Systemverilog , vera , specman...

[jasonxie]

Based on what I know, Vera would be fully integrated into VCS since Version 7.2 (Q2/04), which means free of license fee. So my boss would not like to change from Vera to E.

 

[weilijun]

Vera is easy to learn and use.
In the future, if the main simulator can support SystemVerilog3.1, SystemVerilog is sure to play an important part in the verification field.

 

[harrysoin]

i don't think vera in the future ,

 

[semicon]

i use systemc in SoC system design now.
it's perfect.

 

[foster_cn]

systemc is for system modelling
vera, specman is for verification
systemverilog is trying to do both.

 

[satya]

Hi,
I just dont understand why these language battles among EDA majors..??
as I see, specman 'e', vera,systemverilog and PSLs( mostly Intel and IBM use) all for verification support. But as for my knowledge, PSLs are very powerful for verification (correct me if i m wrong) coz you can specify certain properties in very simple and in one-liners.

I donno why synopsys is digging it's own pit?? if it pushes forward systermverilog, it loses whatever it has with its vera now )

- satya

 

[zyphor]

system c will dying
and
vera has no support
specman is too expensive

So we are waiting systemverilog

 

[beta0]

In our company ,we use systemc for system level
design and verification , it's work so good and make
hardware engineer and software engineer understanding eachother more effictively!

 

[radix]

Check out:

**broken link removed**

It's an article from the 2/5/04 issue of EDN entitled "The search for the perfect language". Good history and overview of the various HDLs. Click on the link for Table1 to get a PDF with a decent side-by-side comparison of some of the features of the different languages.

 

[edacw]

SystemVerilog is very good!

 

[amarnath]

i think ultimately system c will win the race...

 

[blacklancer]

I think systemverilog is better,but it need some days to popularize.
specman need support of EDA tool vendor.

 

[Bajaj]

combination of system c and system verilog

 

[bagane]

I think SystemC is better

 

[lemon]

I also prefer to system verilog

 

[bbtjacking]

As well as I know,SystemC is best for system level and RTL verificaion. And some company, such as Cadence and Synopsys will be focus on this field. For instance, in order to make systemc better for verification, Cadence extend the systemc into CVE according to join some Randomization and concurrency verification methodology and functions into systemc library.

 

[u571]

I think systemC is better, for good interface with C++/C.

 

[omara007]

anyone can direct me to where i can download any e-book for systemC ?

I have heard that there is a good one called (System Design with SystemC) .. is it available here on servers ? .. or even anywhere on the internet ?

 

[ramesh]

SystemVerilog is very good!

Please give reasons whenever you say "it is very good" when compared with others. Otherwise the post may be classified as "useless post" by Moderators!

 

[reddy]

VERA is Better in my opinion. Because, it is having all the OOP features. Moreover I did not use others.
So, no comment on other lang.