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# How to write a 'req' before 'ack' systemverilog assertion?

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#### ash72

##### Newbie level 5
I am not able to write an assertion for the following spec.

$rose(req) must not arrive more than 3 times before$rose(ack) arrives. The \$rose(ack) should arrive within 16 clocks.

Help!!!

Thanks much.

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