SystemC , Systemverilog , vera , specman...

[foster_cn]

Any of them, depends on the projects

 

[zwj_seu]

I'm using specman now.It maybe hard to learn at the beginning,but it's powerful !

 

[zhangpengyu]

Specman is best!

 

[ram]

Now a days many companies are prefering systemc over e....
The reason is simple...the clint which they are going to suplly may not have specman licence...and systemc is free

 

[yerics]

Just as ram said , specman is too expensive , but it is a very great tool.
our boss decide to not purchase specman license any longer next year.

HHH
we will have to use other ...to do verification work
may be systemC

Now a days many companies are prefering systemc over e....
The reason is simple...the clint which they are going to suplly may not have specman licence...and systemc is free

 

[mami_hacky]

Umm, I studied all of the messages here. the result, I think is to use SystemC and SystemVerilog. and to leave e, and vera. Yes?

SystemC is now supported by both of synopsys and cadence, however, no other languge here has such a propery.

correct?

 

[seasonyangd]

If you have experience with c/c++ programming. I suggest you SystemC. You can use it fluently. Cadence Incisive had integerated teh GDB into their debug env (I have not test it). Also, you can use TXE to analyse the data base and do function coverage analysis.

 

[sansprint]

hello ,can i ask you some question about openvera?

hi,Can you tell me something about it ?I had studied it for a month,but i really don't know how to write a programe,can you tell how to write ?Thank you very much!

 

[omara007]

Re: hello ,can i ask you some question about openvera?

hi,Can you tell me something about it ?I had studied it for a month,but i really don't know how to write a programe,can you tell how to write ?Thank you very much!

try a simple program .. chose a very simple one .. like a module with one input port and one output port .. chosen any style in the literature for coding .. and make one process .. let it be sc_method for example .. and in the cpp file write one statement .. cout << " Hi" ..

then if it works .. try to append something .. make some cin's .. try some if condition statements ... then upgrade urself to sc_thread .. try waits ..

u can also go to www.systemc.org and just listen to the discussions ..

 

[rakeshnunna]

In my opinion System Verilog is the most promising

 

[nanako]

systemverilog does look promising as if you look at the LRM, basically it could do almost everything under the sun but the current support by the EDA vendor on their simulator with systemverilog is still far from what the standard is capable of doing.

 

[jjww110]

systemverilog will win in the future!!

 

[sansprint]

omara007,thank you for you tell me so much !Because my english is so bad ,so i don't konw how to express my question,i'm so sorry!:|but can anyone give me an example: a verifiction program write by openvera?a very simple one .thank you very much !

 

[cnspy]

Cadence does not support systemverilog very well. I am testing the assertion of SV. But ncsim does not support such as: not and clock edge between sequence .

 

[dqsh06]

It is a very old topic, i think. now Cadence has perchased verisity. so E language (specman) can be a good choice for verification. Systemc is not a verification language, it is for system modeling.
Vera, PSL　are all verification language.

 

[zcg]

I think specman 'e' is good!

First, it's a mature verification language and excellent support from verisity. Maybe, verisity is only a little-boy so they have to do good support.

Second, it's a aspect-oriented language, easy to use and you can extend new funcionalities easily.

Anyway, who likes to be verification engineer? It's hard to find a job as a verification engineer in the north american. It is better to be ASIC designer rather than verification engineer.

8O

First ,specman E is good but not generally supported by other EDA company. System C and system verilog maybe have more bright future to be common standard.

Second, I think you have a wrong idea of verification job. In fact a good verification engineer should have more knowledge than RTL engineer. Many of them are tranfered from skilled design engineers.

 

[soccer]

vera is too hard to learn.
e is most popular
systemverilog is most hopeful

 

[nittinsharma80]

SystemVerilog is the FUTURE

 

[omara007]

SystemVerilog is the FUTURE

I guess SystemVerilog is suffering the same problem that Verilog suffers .. being slow .. compared to C .. or specifically SystemC ..

 

[nittinsharma80]

But it has more powerfull features than SystemC and is being used more in the industry