the following diagram basicly illustrates the SystemVerilog and other languages's development flow:
in addition, since SystemVerilog and SystemC are open languages and have many tool vendors to support them such that you're not restricted to only one tool vendor, which can bring you much flexibility and freedom.
in my opinion, proprietary languages such as e and openvera will doom to go to die.
currently many tool vendors such as Mentor and synopsys and other vendors has supported all or many of the features provided by Systemverilog. and SystemC is widely supported among the eda tool vendors, which is fundamentally a modeling language which leverage your modeling efficiency.
all the materials about SystemVErilog can be searched in the web of [url]www.accellera.com[/url], SystemVerilog is presided by this organization.