SystemC , Systemverilog , vera , specman...

[pandey.kapil@gmail.com]

vera and specman LRM

Hi,

who go get the LRM of specman and vera?

Added after 13 minutes:

Hi

How i can learn specman,I realy want to learn this.
So kindly inform me how go get LRM or any document related to specman


Thanks

 

[Thomson]

the following diagram basicly illustrates the SystemVerilog and other languages's development flow:


in addition, since SystemVerilog and SystemC are open languages and have many tool vendors to support them such that you're not restricted to only one tool vendor, which can bring you much flexibility and freedom.

in my opinion, proprietary languages such as e and openvera will doom to go to die.

currently many tool vendors such as Mentor and synopsys and other vendors has supported all or many of the features provided by Systemverilog. and SystemC is widely supported among the eda tool vendors, which is fundamentally a modeling language which leverage your modeling efficiency.


all the materials about SystemVErilog can be searched in the web of [url]www.accellera.com[/url], SystemVerilog is presided by this organization.

 

[brianhe]

Specman is great but also expensive.
System verilog is well defined but sill not mature and well supported

 

[sansprint]

you can go to synopsys'free download,there is lrm

 

[ldm]

sansprint, where can I download OpenVera or SystemVerilog?

 

[hayang]

i don't know why someone said "systemVerilog is slow", from general understanding, using any third party EDA tool will make the simulator slow. But if we use systemVerilog we don't need any third-party tool through PLI interface. so, using systemVerilog is faster. is my understanding correct?

 

[asilic]

in my company,now using E ,vera and systemC ,but not systemverilog,is there any tools support systemverilog now?

 

[vikadik]

All major companies like cadence ( SOC encounter ), Magma have updated there tools for using SV.

 

[ljxpjpjljx]

now SV is very popular for verification and design !
SystemC can be very useful for agrithem modeling!

 

[xdmicro]

i am waiting systemverilog