linny_chen
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design compiler alu
Hi, friends,
I have a simple HDL model which I want to synthesize with Design compiler. It looks like this:
The output of an ALU is connected to a flip-flop. At the same time, the output of ALU is bypassed by another signal. Both the registered output and bypassed output are connected to a 2-to-1 multiplexer. You don't need to care about what circuit is before the ALU input or after the multiplexer output.
The current problem is that, when I want to synthesize the whole circuit, the design compiler will take the bypass circuit and keep on accumulating the critical path with the circuit after the multiplexer. But what I really need is to make the design compiler stop accumulating the critical path at the register and don't touch the bypass. Is there any way or commands to realize that?
Thanks very much!
regards
Hi, friends,
I have a simple HDL model which I want to synthesize with Design compiler. It looks like this:
The output of an ALU is connected to a flip-flop. At the same time, the output of ALU is bypassed by another signal. Both the registered output and bypassed output are connected to a 2-to-1 multiplexer. You don't need to care about what circuit is before the ALU input or after the multiplexer output.
The current problem is that, when I want to synthesize the whole circuit, the design compiler will take the bypass circuit and keep on accumulating the critical path with the circuit after the multiplexer. But what I really need is to make the design compiler stop accumulating the critical path at the register and don't touch the bypass. Is there any way or commands to realize that?
Thanks very much!
regards