Synthesize question about design composed of several modules

[gogogo]

synthesize question:
i have a design composed of several modules,
and some modules are modified, when synthisize it with the same script, i found
the areas of the modules which i did not modify changed!!!
why???

 

[spauls]

Re: synthesize question

Please mail , me,
i will give you a script which automatically goes into each module and get the area of chip.
you can run on your earlier design and new design and after that compare same .
For security reasons i cant put code in foroum.

 

[roger]

Re: synthesize question

synthesize question:
i have a design composed of several modules,
and some modules are modified, when synthisize it with the same script, i found
the areas of the modules which i did not modify changed!!!
why???

compile the unchanged module to .db file
open the .db file to your top script
link them
set current design at top module
compile them
then the unchanged module won't be different!

 

[tony_taoyh]

synthesize question

I think, for new version of DC< there provide the function of optimization accross boundary.

This may be the reason;

actually, you can use eye to check the logic between port.

Maybe, formality can be used to check it;

 

[ceyjey]

Re: synthesize question

If you synthesize your modules in a hierarchical way and set_dont_touch to the modules you don't want to be changed, the result should go as what you expected. How ever this might not be the optimized results, DC is able to optimize the module boundaries according to the changes in the load and logics.

 

[sandusty]

synthesize question

The I/Os' loads/driven strength of the modified module will change, so need to optimized the connected modules...

 

[kshitij_s81]

Re: synthesize question

We can synthesize the modules by bottom up compile because then we can just characterize the lower sub module and know the environment surrounding the submodule block and hence we can constrain the design more accurately