May 20, 2011 #1 H Hallolo Newbie level 3 Joined Apr 1, 2011 Messages 4 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,307 Hi what is a synthesizable form of : counter_out <= #12 counter_out + 1; in verilog HDL, where i intend to replace 12 by generic code that performs a count and hold for some number of clock cycles. Thanks
Hi what is a synthesizable form of : counter_out <= #12 counter_out + 1; in verilog HDL, where i intend to replace 12 by generic code that performs a count and hold for some number of clock cycles. Thanks
May 21, 2011 #2 P permute Advanced Member level 3 Joined Jul 16, 2010 Messages 918 Helped 295 Reputation 590 Reaction score 266 Trophy points 1,343 Activity points 8,543 that probably isn't what you want. synthesis will ignore the time delay. always@(posedge clk) begin // also add the resets, not shown here. x <= (x == 12) ? 1 : x+1; y <= (x == 12) ? y+1 : y; end Click to expand...
that probably isn't what you want. synthesis will ignore the time delay. always@(posedge clk) begin // also add the resets, not shown here. x <= (x == 12) ? 1 : x+1; y <= (x == 12) ? y+1 : y; end Click to expand...