Hallolo
Newbie level 3
Hi
what is a synthesizable form of : counter_out <= #12 counter_out + 1;
in verilog HDL, where i intend to replace 12 by generic code that performs a count and hold for some number of clock cycles.
Thanks
what is a synthesizable form of : counter_out <= #12 counter_out + 1;
in verilog HDL, where i intend to replace 12 by generic code that performs a count and hold for some number of clock cycles.
Thanks