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synthesizable counter with delay

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Hallolo

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Hi

what is a synthesizable form of : counter_out <= #12 counter_out + 1;
in verilog HDL, where i intend to replace 12 by generic code that performs a count and hold for some number of clock cycles.

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permute

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that probably isn't what you want. synthesis will ignore the time delay.
always@(posedge clk) begin // also add the resets, not shown here.
x <= (x == 12) ? 1 : x+1;
y <= (x == 12) ? y+1 : y;
end
 

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