[SOLVED] synthesis problem on Design Compiler

[yushionly]

I am a new user,when i use design compiler for synthesis a simple full adder example, the result got me puzzled.
result:
Point Incr Path
-----------------------------------------------------------
clock clk (rise edge) 0.00 0.00
clock network delay (ideal) 0.00 0.00
input external delay 0.00 0.00 r
ci (in) 0.00 0.00 r
U9/Y (XNOR3X4) 0.83 0.83 r
U10/Y (CLKINVX20) 1.48 2.31 f
s (out) 0.00 2.31 f
data arrival time 2.31

why the time delay is so long? 2.31ns? anyone could explain it?thanks!

code:
module adder(a,b,ci,s,co);
input a,b,ci;
output s,co;

assign s=(a&(~ci)&(~b))|(a&b&ci)|((~a)&(~ci)&b)|((~a)&(~b)&ci);
assign co=(a&b)|(a&ci)|(b&ci);

endmodule

constrain.tcl:
# specify your logic delay here (in nanosecend)
set DELAY 0
set CLK "clk"; #virtual clock name

create_clock -name $CLK -period $DELAY
set MAX_LOAD [load_of umc18io3v5v_slow/P8A/P]
set_input_delay 0 -clock $CLK [all_inputs]
set_driving_cell -lib_cell P8A -pin P [all_inputs]
set_max_capacitance $MAX_LOAD [all_inputs]
set_output_delay 0 -clock $CLK [all_outputs]
set_load [expr $MAX_LOAD * 2] [all_outputs]
set_max_area 0
set_operating_conditions -max "slow" -max_library "slow" -min "fast" -min_library "fast"
set auto_wire_load_selection false
set_wire_load_model -name umc18_wl20 -library slow
set_wire_load_mode top

 

[reasly]

You got too large load set on output port.
umc18io3v5v_slow/P8A/P is apparently a pad cell's pad , which connect bonding wires. This load is too large for cells inside the chip.
If you mean the output pin of your adder is to drive a pad cell, you should use the pin umc18io3v5v_slow/P8A/{some other pin that connect on chip net}

 

[yushionly]

Thanks a lot ! I will have a try