Synthesis of STATE machine Verilog

[ashgun]

Hi all i want to know about the sythesis of state machine in verilog . basically we say that CASE statement synthesizes multiplexer and we use CASE statement in STATE MACHINES also so can any body tell me the what it will look like in Hardware means using muxes gates or some higher level blocks . Can anybody give a diagram with these blocks , can take any small state machine .

 

[rameshsuthapalli]

Hi,

The case statement will be converted into the MUX usually but in some cases if u have some complex library cells with which we can implement the same case statement and have less delay compared to MUX then the tool will take that complex cell and it will implement the logic.

regards,
ramesh.s

 

[vinodkumar]

Hi
I know that when we synthesize we will get netlist for the code written,but is it fixed tht for case statemnt we get MUX etc,if so can you plz provide documents for tht becoz it turns good intervies question to expect the HW.

bye.