[Synthesis] Area Constraints

[ivlsi]

Hello All,

For the Logic Synthesis, is there a sense to define an area constraint, which would be different from '0'? Will it help in Timing Closure? As far as I remember, the tool firstly work on the timing optimization and only then on area...

Is a Floorplan usually done before or after the Logic Synthesis?

Thank you!

 

[yadavvlsi]

Area constraints to tool is given have lesser area. It doesn't help in meeting timing. Tool does upsizing and buffer insertion to meeting timing, this will cause increase in area. Yes, meet timing is always first priority for the tool. Floorplan is normally after synthesis. But if you are doing physical synthesis then floorplan is done before synthesis. Physical Synthesis is where the synthesis flow makes use of its knowledge of the physical layout and timing of the target device in order to achieve the minimum area usage at the required speed.
https://www.cse.unl.edu/~seth/990/Pubs/What is physical synthesis.pdf

 

[ivlsi]

How a floorplanning / layout might be done before a logic synthesis without a knowledge of number of cells and memories implemented in the RTL code?

 

[yadavvlsi]

First you have to do normal synthesis and create a floorplan. Then this floorplan will be given as input to physical synthesis.

 

[ivlsi]

Could a not-realistic area constraint (let's say 'max_area 0') have a negative effect on the timing closure? If this is not a csae, then why always not to define 0 area for the synthesis? When and why does it start making a sense?
Thank you!

 

[englishdogg]

Timing is always the first priority of the tool over area .. only once timing is met it starts recovery towards area nd power. Even if you set it to "0" do you believe that is possible.. NO.. the same we still do to leakage power setting as 0 but thats not possible.
Its is just the way it is to tell tools to go full-throttle toweards more aggressive optimization.

Also max_area as a constraint is not accepted by Cadence tools from my knowledge but Synopsys takes it well.
It is more or less just a ball-park figure that is crafted depending on the core size available as a constraint

 

[ivlsi]

"max_area 0" - what's its analogy for Cadence tools?

 

[englishdogg]

As i mentioned before to my knowledge it does not have anything to understand / accept this term / construct
They ahve different ways to save area and also claim primarily their engine should do it as a part of global synthesis that they offer and i have seen it do a good job in most of the cases.

If you look at it the other way there will never be a max_area 0 or any number that you set - what logic/function is there in the RTL has to be mapped to logic gates.
To get a realistic numebr to this - according to me requries quite a few trials

 

[ivlsi]

this floorplan will be given as input to physical synthesis

What's constrain comes from Floorplaning to the physical synthesis? Area? Geometry? How should the design be constrained to a specific area?
Does Floorplaning also include P&R? What's output/results from Floorplaning?
What files/constrains provided from Floorplaning tools to Synthesis tools? What format of the info (SDC, others)?
Why is it so important to do Floorplaning in prior to Logic Synthesis?

 

[dftrtl]

Synthesis can be done without floorplan also. Now DC supports DC topographical synthesis with placement details.

 

[englishdogg]

@dmitryl

Basicaly die area, shrink factor, standard cell arearegions, guides fences macro / pad locations, oprientation etc is mentioned in the floorplan def for physical synthesis etc
The standard cell area or also termed as core area available in the FPDEF is considered as the area constraint

Floorplaning is the initial step of P&R - it is on this floorplan that the design is placed, optimized, bukd clock tree and then routed
Only the best floorplan goes into the synthesis tool - .def is the industry standard but all vendars have their own format as well.

I would not say priori to logic synthesis - but it is important to have a floorplan for physical synthesis. Without an initial netlist you cannot have a floorplan until it is a derivative design. Or you have a clear spec of the die size and brak of core area vs macro area