synopsys vcs vhdl and verilog mix simulation

wu8d · May 30, 2010

Does any one know how to do synopsys vcs vhdl and verilog mix simulation?
I cannot find any tutorial or document about that.
so if anybody know
please write the correct document/tutorial name.
I have search the internet for days.
but only discussion, no exact answers.

I know it should support that. But I don't know how to do.
There are command parameter in vcs
Any one give me a successful tutorial?

I'm using the default lib.
the default lsi_10k lib needs mix simulation.

Added after 3 minutes:

Typically when doing post synthesis simulation.
I cannot compile the simulation because it needs lsi_10k lib, which is described by vhdl.

jassen · Jul 16, 2010

About the MIX simulation, you can get more flow from the VCS manual.
1. You should create the *.setup file;
2. You should compile VHDL/Verilog into lib folder such as work
3. Add +vhdllib+work parameters
etc.

You can reference the VCS manual.

synopsys vcs vhdl and verilog mix simulation

wu8d

Newbie level 1

jassen

Newbie level 6

Similar threads

synopsys vcs vhdl and verilog mix simulation

wu8d

Newbie level 1

jassen

Newbie level 6

Similar threads

Privacy & Transparency

Privacy & Transparency